Liquid crystal display device and method of driving the same

• US 4,955,697 A
• Filed: 04/19/1988
• Issued: 09/11/1990
• Est. Priority Date: 04/20/1987
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kaneko, Yoshiyuki, Sasano, Akira, Tsukada, Toshihisa
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Mai, Huy K.
• Application Number:
  US07/183,141
• Time in Patent Office: 875 Days
• Field of Search: 350/332, 350/333, 350/334, 340/784, 340/805
• US Class Current: 349/38
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2320/0204 Compensation of DC component across the pixels in flat panels
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A liquid crystal display panel and a method of driving the display panel are disclosed. The display panel and the driving method can reduce the leakage of a gate driving voltage to a first pixel electrode due to the parasitic capacitance of a thin film transistor, and can lessen an adverse effect of noise which is generated at a second pixel electrode by cancelling out the capacitive coupling to the first pixel electrode, on an image displayed by the display panel.

Claims

1. A liquid crystal display panel comprising:

a first substrate;

a second substrate having a transparent conductive film thereon;

a liquid crystal layer sandwiched between the first and the second substrates;

a plurality of pixel electrodes formed on the first substrate and associated with respective intersections of parallel rows and parallel columns wherein the rows comprise a plurality of gate lines and the columns comprise a plurality of data lines;

a plurality of thin film transistors formed on the first substrate for driving the pixel electrodes, respectively, each transistor having a gate connected to an associated gate line and two electrodes one of which is connected to one of the plurality of pixel electrodes and another electrode is connected to an associated data line;

the plurality of gate lines being driven successively in a predetermined order for on-off control of the thin film transistors, each of the pixel electrodes in each one row being made to overlap the gate line in another row adjacent to the one row so as to provide capacitive coupling between the overlapping pixel electrode and the gate line;

wherein the capacitive coupling between the overlapping pixel electrode and the gate line is represented by a capacitance C_add which satisfies the following formula;

space="preserve" listing-type="equation">C.sub.add =(V.sub.1 /V.sub.2)Cgs

where Cgs indicates a parasitic gate-source capacitance of the thin film transistor;

means for applying a driving voltage to each one of the plurality of gate lines, the driving voltage having a waveform which is at a voltage level V_ON when the thin film transistors connected to said one gate line are to be ON-state, at a voltage level V_OFF when said thin film transistors are to be OFF-state, and a voltage level V_COMP just before said driving voltage goes up to the voltage level V_ON and when the driving voltage applied to the precedingly driven gate line is at the voltage level V_ON, where V_ON >

V_OFF >

V_COMP.

2. A liquid crystal display panel comprising:

a first substrate;

a second substrate having a transparent conductive film thereon;

a liquid crystal layer sandwiched between the first and the second substrates;

a plurality of pixel electrodes formed on the first substrate and associated with respective intersections of parallel rows and parallel columns wherein the rows comprise a plurality of gate lines and the columns comprise a plurality of data lines;

a plurality of thin film transistors formed on the first substrate for driving the pixel electrodes, respectively, each transistor having a gate connected to an associated gate line and two electrodes, one of which is connected to one of the plurality of pixel electrodes and an other electrode is connected to an associated data line;

the plurality of gate lines being driven successively in a predetermined order for on-off control of the thin film transistors, each of the pixel electrodes in each one row being made to overlap the gate line which is to be driven after the gate line in another row adjacent to the one row so as to provide capacitive coupling between the overlapping pixel electrode and the gate line, wherein said capacitive coupling between the overlapping pixel electrode and the gate line is represented by a capacitance C_add which satisfies the following formula;

space="preserve" listing-type="equation">C.sub.add =(V.sub.1 /V.sub.2)·

C.sub.gs

where C_gs indicates a parasitic gate-source capacitance of the thin film transistor; and

,

means for applying a driving voltage to each one of the plurality of gate lines, the driving voltage having a waveform which varies a voltage value v₁ at an off time when the thin film transistors controlled by that driving voltage are to be rendered off, and also varying a voltage value (v₁ +v₂) in a direction opposite to that of the voltage v₁ at a time corresponding to the off time for the thin film transistors controlled by one of the gate lines driven preceding to that one gate line presently driven, where v₁ >

0 and v₂ >

0.

3. A liquid crystal display panel comprising:

a first substrate;

a second substrate having a transparent conductive film thereon;

a liquid crystal layer sandwiched between the first and the second substrates;

a plurality of pixel electrodes formed on the first substrate and associated with respective intersections of first to n-th parallel rows and parallel columns, where n is an integer and wherein the rows comprise a plurality of gate lines and the columns comprise a plurality of data lines;

a plurality of thin film transistors formed on the first substrate for driving the pixel electrodes, respectively, each transistor having a gate and two electrodes one of which is connected to one of the plurality of pixel electrodes and an other electrode is connected to an associated data line;

wherein the plurality of gate lines include a plurality of first to n-th gate lines formed on the first substrate corresponding to the first to the n-th rows of the pixel electrodes, respectively, each one of the plurality of gate lines, generally represented by (i-th) gate line where i is an integer satisfying 1≦

i≦

n, being connected to the gates of the thin film transistors associated with the pixel electrodes disposed in the i-th row and the gate lines being driven successively in an order of the first to the n-th gate line for on-off control of the thin film transistors connected to the gate lines, wherein each of the pixel electrodes disposed in the i-th row overlaps the (i+1)-th gate line so as to provide capacitive coupling between the overlapping pixel electrode and the gate line;

wherein said capacitive coupling between the overlapping pixel electrode and the gate line is represented by a capacitance C_add which satisfies the following formula;

space="preserve" listing-type="equation">C.sub.add =(V.sub.1 /V.sub.2)·

C.sub.gs

where C_gs indicates a parasitic gate-source capacitance of the thin film transistor; and

,

means for applying to the (i+1)-th gate line a driving voltage having a waveform which varies a voltage value v₁ at an off time when the thin film transistors controlled by that driving voltage are to be turned off and also varies a voltage value (v₁ +v₂) in a direction opposite to that of the voltage v₁ at a time corresponding to the off time for the thin film transistors controlled by the i-th gate line, where v₁ >

0 and v₂ >

0.

4. The liquid crystal display panel according to claim 3, wherein the voltage change (v₁ +v₂) in the gate driving voltage applied to the (i+1)th gate line is generated substantially simultaneously with the voltage change v₁ in the gate driving voltage applied to the i-th gate line.

5. The liquid crystal display panel according to claim 3, wherein the voltage change (v₁ +v₂) in the gate driving voltage applied to the (i+1)th gate line is generated at a time less than a predetermined time interval during which the thin film transistor is to be at ON-state after generation of the voltage change v₁ in the gate driving voltage applied to the i-th gate line.

6. A method of driving a liquid crystal display panel comprising a first substrate;

a second substrate having a transparent conductive film thereon;

a liquid crystal layer sandwiched between the first and the second substrates;

a plurality of pixel electrodes formed on the first substrate and associated with respective intersections of first to n-th parallel rows and parallel columns, where n is an integer, and wherein the rows comprise a plurality of gate lines and the columns comprise a plurality of data lines;

a plurality of thin film transistors formed on the first substrate for driving the pixel electrodes, respectively, each transistor having a gate and two electrodes one of which is connected to the associated pixel electrode; and

an other electrode is connected to an associated data line;

wherein the plurality of gate lines include a plurality of first to n-th gate lines formed on the first substrate corresponding to the first to the n-th rows, respectively, each gate line, generally represented by (i-th) gate line where i is an integer satisfying 1≦

i≦

n, being connected to the gates of the thin film transistors associated with the pixel electrodes disposed in the i-th row and the gate lines being driven successively in an order of the first to the n-th gate line for on-off control of the thin film transistors of which the gates are connected to the gate line as driven;

each of the pixel electrodes disposed in the i-th row overlapping with the (i+1)-th gate line so as to provide capacitive coupling between the overlapping pixel electrode and the gate line, wherein said capacitive coupling between the overlapping pixel electrode and the gate line is represented by a capacitance C_add which satisfies the following formula;

space="preserve" listing-type="equation">C.sub.add =(V.sub.1 /V.sub.2)·

C.sub.gs

where C_gs indicates a parasitic gate-source capacitance of the thin film transistor, said method comprising the steps of;

applying to the i-th gate line a first driving voltage which varies a voltage value v₁ at an off time for turning off the thin film transistors whose gates are connected to the i-th gate line; and

applying to the (i+1)-th gate line a second driving voltage having a wave form which varies, at a time corresponding to the off time for the gate voltage applied to the i-th gate line a voltage value (v₁ +v₂) in a direction opposite to that of the voltage v₁, where v₁ >

0 and v₂ >

0.

7. A method of driving a liquid crystal display panel, as claimed in claim 6, wherein the voltage change (v₁ +v₂) in the gate driving voltage applied to the (i+1)th gate line is generated substantially simultaneously with the voltage change v₁ in the gate driving voltage applied to the i-th gate line.

8. A method of driving a liquid crystal display panel, as claimed in claim 6, wherein the voltage (v₁ +v₂) in the gate line is generated at a time less than a predetermined time interval during which the thin film transistor is to be at ON-state after generation of the voltage change v₁, in the gate driving voltage applied to the i-th gate line.