Thin oxide sidewall insulators for silicon-over-insulator transistors

• US 4,956,307 A
• Filed: 11/10/1988
• Issued: 09/11/1990
• Est. Priority Date: 11/10/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pollack, Gordon P., Sundaresan, Ravishankar, Matloubian, Mishel
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Holtzman, Laura
• Application Number:
  US07/269,803
• Time in Patent Office: 670 Days
• Field of Search: 437/62, 437/40, 437/238, 437/244, 437/968, 437/978, 437/938, 148/DIG. 86, 148/DIG. 150
• US Class Current: 438/165
• CPC Class Codes: H01L 21/32105 Oxidation of silicon-containing layers
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: Y10S 257/906 Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
• CPC Class Codes: Y10S 438/911 Differential oxidation and etching
• CPC Class Codes: Y10S 438/953 Making radiation resistant device

Abstract

A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa'"'"'s insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

Claims

1. a method of forming a radiation hard transistor comprising:

forming a mesa from semiconductor material;

forming an insulated region adjacent to said mesa;

forming a conforming oxidizable layer on the sides of said insulator region;

anisotropically etching said oxidizable layer; and

oxidizing said oxidizable layer to create oxide sidewalls.

2. The method of claim 1 wherein said step of forming an insulator region comprises the step of forming an oxide encompassing said mesa.

3. the method of claim 1 wherein said step of forming an oxidizable layer comprises forming an amorphous silicon layer.

4. the method of claim 3 wherein said step of forming an amorphous silicon layer comprises the step of forming a doped amorphous silicon layer.

5. the method of claim 1 wherein said step of forming an oxidizable layer comprises forming a polysilicon layer.

6. The method of claim 5 wherein said step of forming a polysilicon layer comprises the step of forming a doped polysilicon layer.

7. the method of claim 1 wherein said step of forming said oxide sidewalls further comprises forming a foot at the bottom edge of said sidewalls.

8. the method of claim 7 wherein said step of forming said foot and said step of anisotropically etching said oxidable layer comprises:

forming TEOS layer over said oxidizable layer;

anisotropically etching said TEOS layer and said oxidable layer; and

removing said TEOS layer in order to define said foot at the bottom edge of said sidewall.

9. a method of forming a transistor comprising:

forming a mesa from semiconductor material;

forming an insulator region encompassing said mesa;

forming a conforming oxidable layer on said insulated region;

forming a conforming spacer layer on said oxidable layer;

anisotropically etching said spacer layer and said oxidable layer;

removing said spacer layer; and

oxidizing said oxidizable layer to create oxide walls.

10. The method of claim 9 wherein said step of forming an oxidable layer comprises forming an amorphous silicon layer.

11. the method of claim 10 wherein said step of forming an amorphous silicon layer comprises forming doped amorphous silicon layer.

12. The method of claim 9 wherein said step of forming an oxidable layer comprises forming a polysilicon layer.

13. The method of claim 12 wherein said step of forming a polysilicon layer comprises forming a doped polysilicon layer.

14. The method of claim 9 and further comprising forming a gate over said insulator region.

15. The method of claim 9 wherein said spacer layer comprises silicon dioxide.

16. The method of claim 15 wherein said spacer layer comprises TEOS silicon dioxide.