Method of making self-aligned field-effect transistor

• US 4,956,308 A
• Filed: 01/20/1987
• Issued: 09/11/1990
• Est. Priority Date: 01/20/1987
• Status: Expired due to Term

• Current Assignee: Tyco Electronics Logistics AG (TE Connectivity Limited)
• Original Assignee: ITT Corporation (ITT, Inc.)
• Inventors: Sadler, Robert A., Griffin, Edward L., Geissberger, Arthur E.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): QUACH, TUAN N
• Application Number:
  US07/004,992
• Time in Patent Office: 1,330 Days
• Field of Search: 29/571, 29/578, 29/580, 357/22, 357/23, 357/15, 437/40, 437/41, 437/45, 437/39, 437/912
• US Class Current: 438/179
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66878 Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: Y10S 148/105 Masks, metal
• CPC Class Codes: Y10S 148/106 Masks, special

Abstract

A self-aligned gate (SAG) transistor or FET is described which transistor overcomes several disadvantages of the prior art for making SAG field-effect transistors. The disadvantages noted above result from the fact that current SAG FET'"'"'s have a symmetrical structure, with n+ regions on either side of the gate electrode. This invention provides a means of masking off a region on the drain side of the gate electrode before performing an n+ implant, so that the n+ implanted region is asymmetrical on the two sides of the gate electrode. This has the desired beneficial effect of reducing the parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, and output resistance that invariably accompany a high doping level on the drain side of the gate. Using this technique, substantially increased performance can be obtained from a self-aligned FET.

Claims

1. An improved GaAs FET manufacturing process including the ordered steps of:

(a) providing a substrate comprising a GaAs region on a first major surface of said substrate, said GaAs region including a channel region;

(b) providing a gate over said channel region, said gate having a first lateral edge and a second lateral edge;

(c) providing an implant mask extending laterally over said channel region beyond said second lateral edge of said gate, said mask having source and drain implant openings; and

(d) introducing impurities via said implant openings into said GaAs region to form source and drain regions, said drain region laterally spaced from said second lateral edge of said gate as a result of said lateral extension of said mask wherein said step of providing an implant mask extending laterally over said channel region beyond said second lateral edge of said gate comprises;

providing a layer of photoresist over said substrate; and

patterning said photoresist such that said photoresist extends laterally over said channel region beyond said second lateral edge of said gate and does not extend laterally over said channel region beyond said first lateral edge of said gate.