Interconnect structure for integrated circuits

• US 4,956,749 A
• Filed: 11/20/1987
• Issued: 09/11/1990
• Est. Priority Date: 11/20/1987
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Chang, Cheng-Cheng
• Primary Examiner(s): Thompson, Gregory D.
• Application Number:
  US07/123,488
• Time in Patent Office: 1,026 Days
• Field of Search: 174/68.5, 361/386-389, 361/397, 361/404, 361/406, 361/412, 361/414, 29/840, 29/850
• US Class Current: 361/795
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 7/06 on insulating boards , e.g. wiring harnesses for printed circuits H05K1/18, H05K3/30
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49162 by using wire as conductive path

Abstract

A semiconductor integrated device support structure having a transmission line interconnect structure in a metal block on which the devices are mounted. The metal block is formed photolithographically from layers which define X,Y sections of the block. A plurality of stacked layers contains the complete wireline interconnect network. Each wire is a true coaxial transmission line having an inner conductor, a surrounding dielectric material and an outer conductor. By appropriate choice of radii of the inner conductor and the surrounding dielectric material, favorable impedances may be selected.

Claims

1. An interconnection structure for semiconductor integrated circuits comprising,

a substrate having a plurality of electrical terminal members therein,

an electrically conductive metal block disposed over the substrate with a component mounting surface, the metal block containing an electrically conductive wire interconnection pattern, insulated from the metal block, extending from the plurality of electrical terminal members associated with the substrate to the component mounting surface of the block, and

a plurality of semiconductor integrated circuits joined to the wire interconnection pattern at the mounting surface.

2. The interconnection structure of claim 1 wherein wires comprising said wire interconnection pattern have a dielectric material coating coaxially surrounding said wires in the pattern, with said dielectric material coating contacting the metal block.

3. The interconnection structure of claim 2, wherein said wires have an average radius, a, and said dielectric material coating has an average radius, b, wherein the ratio b/a is characteristic of a transmission line having a desired impedance for the selected dielectric material.

4. The interconnection structure of claim 1 wherein said electrical terminal members are pins extending from said substrate and in electrical communication with said wire interconnection pattern.

5. A method of interconnecting finished integrated circuits with a coaxial transmission line network comprising,

(a) building a network of bare electrically conductive wires over a nonconductive substrate in a three dimensional structure extending from chip contact locations to wire terminal members projecting through said substrate at signal interface locations spaced apart from the chip contact locations,

(b) coating the built network of bare wires over said substrate with a selected dielectric material to form a plurality of coaxial transmission lines each having an impedance dependent on the ratio of a diameter of the dielectric material to a diameter of the conductive wires, and

(c) encapsulating the dielectrically coated bare wires with metal.

6. The method of claim 5 further defined by providing said wires with an average diameter a, and said dielectric material coating with an average outer diameter b, where the ratio b/a is characteristic of a respective coaxial transmission line having a desired impedance for said selected dielectric material.

7. The method of claim 5 further defined by terminating the chip contact locations in solder bumps.

8. The method of claim 5 wherein said metal for encapsulating the dielectrically coated bare wires is selected from copper and nickel plating.

9. The method of claim 5 further defined by building said network of wires photolithographically.

10. The method of claim 5 further defined by forming thermally conductive fins in said metal encapsulating said coated wires.

11. The method of claim 5 further defined by building said network of wires one layer upon another.

12. A method for interconnecting finished semiconductor integrated circuits comprising,

providing a substrate having a planar upper surface and a plurality of electrical terminal members therein,

patterning a first planar layer over the planar substrate surface, the pattern comprising resist regions and electrically conductive metal regions, the metal regions communicating with the electrical terminal members and being x,y sections of a three dimensional wire interconnection pattern,

patterning further planar layers, each atop a lower patterned planar layer, the pattern in each layer comprising resist and electrically conductive metal regions and being x,y sections of a three dimensional wire interconnection pattern, the further planar layers defining a z direction for the interconnection pattern wherein x,y and z are orthogonal coordinate directions, the uppermost layer having metal regions in locations corresponding to contact locations of finished semiconductor integrated circuits,

removing the resist from all layers, leaving an exposed electrically conductive metal interconnection pattern,

coating the metal interconnection pattern, with a coaxial sheath of dielectric material, the coating having a thickness sufficient to prevent electrical shorting between the interconnection pattern and subsequent metal plating,

applying metal plating to the dielectric material in a volume forming a support block encapsulating the dielectric coated metal interconnection pattern, and

joining finished semiconductor integrated circuits to exposed metal regions in the upper surface of the uppermost layer.

13. The method of claim 12 wherein said metal regions in each of said planar layers have an average radius, a, and said coaxial sheath of dielectric material coating the metal interconnection pattern has an average radius, b.

14. The method of claim 12 wherein said metal regions in each of said planar layers have an average radius, a, and said dielectric material coating the metal interconnection pattern has an average radius, b, wherein the ratio b/a is characteristic of a coaxial transmission line having a desired impedance for the selected dielectric material.

15. The method of claim 12 wherein said plating is copper or electroless nickel plating.

16. A method of interconnecting finished integrated circuits comprising,

building a network of bare electrically conductive wires in a three dimensional structure extending from chip contact locations to signal interface locations spaced apart from the chip contact locations,

coating the bare wires with a dielectric material to form a plurality of coaxial transmission lines each having an impedance dependent on the ratio of a diameter of the dielectric material to a diameter of the respective conductive wire, and

encapsulating the dielectrically coated bare wires with metal, thereby completing a transmission line network and forming said metal to establish one or more thermally conductive fins.