Counter driven RAM engine control

• US 4,956,781 A
• Filed: 02/15/1989
• Issued: 09/11/1990
• Est. Priority Date: 02/15/1989
• Status: Expired due to Fees

• Current Assignee: Delco Electronics Corporation (General Motors Company)
• Original Assignee: Delco Electronics Corporation (General Motors Company)
• Inventors: Siler, Jimmie R., Calvird, Harry R. II
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/310,174
• Time in Patent Office: 573 Days
• Field of Search: 364/431.04, 364/431.05, 364/431.07, 123/480, 123/486, 123/488, 123/416, 123/417, 377/20
• US Class Current: 701/102
• CPC Class Codes: F02D 41/263 the program execution being modifiable by physical parameters
• CPC Class Codes: F02D 41/36 with means for controlling distribution
• CPC Class Codes: Y02T 10/40 Engine management systems

Abstract

A system provides for controlling various vehicle functions by use of a free-running counter that drives the address lines of a random access memory which are shared with a control microprocessor. The counter represents a clock which directly maps addresses in the RAM to discrete moments in time. Each bit at each RAM memory location describes an on or off control command of a particular function. The microprocessor sets selected bits corresponding to the control function in two address locations corresponding to the on and off points in time so as to enable the generation of a pulse of exact direction for control.

Claims

1. A system for generating a control signal for controlling a predetermined function in timed relationship to the operation of a vehicle engine, the system comprising, in combination:

a memory having a plurality of addressable memory locations;

addressing means for (A) generating sequential memory addresses in a predictable sequence and at a predetermined frequency and (B) addressing the memory locations in the memory by the generated sequential memory addresses, the memory providing an output control signal corresponding to a stored digital signal at the addressed memory location;

means for generating a reference signal representing a predetermined operating condition of the engine; and

means responsive to the generation of the reference signal for (A) sampling the memory address generated by the addressing means, the sampled memory address representing the time of occurrence T₀ of the reference signal, (B) determining a desired delay from the time T₀ for controlling the predetermined function, (C) determining the memory address that will be generated by the addressing means at a future point in time spaced from the time T₀ by the desired delay, and (D) storing a digital control signal in the memory at the memory location addressed by the determined memory address, whereby the output control signal corresponding to the stored digital control signal will be provided by the memory at a time T₁ spaced from the time T₀ by the desired delay.

2. A system for generating a control signal for controlling a predetermined function in timed relationship to the operation of a vehicle engine, the system comprising, in combination:

a memory having a plurality of addressable memory locations;

clock means for generating clock signals at a predetermined frequency;

a free running counter clocked by the clock signals and providing a count output that is incremented at the predetermined frequency;

means for addressing the memory locations in the memory by the count output of the counter, the memory providing an output signal corresponding to a stored digital signal at the addressed memory location;

means for generating a reference signal representing a predetermined operating condition of the engine; and

means responsive to the generation of the reference signal for (A) sampling the count output of the counter, the sampled count output representing the time of occurrence T₀ of the reference pulse, (B) determining a desired delay in terms of the number of clock signals generated by the clock means from the time T₀ for controlling the predetermined function, (C) summing the determined delay with the sampled count to determine the memory location to be addressed by the count output of the counter at a time T₁ spaced from the time T₀ by the desired delay, and (D) storing a digital control signal in the memory at the determined memory location to be addressed at the time T₁, whereby the output control signal corresponding to the stored digital control signal will be provided by the memory at the time T₁.

3. A system for energizing a fuel injector of an internal combustion engine in timed relationship to the rotation of the engine, the system comprising, in combination:

a memory having a plurality of addressable memory locations;

clock means for generating clock signals at a predetermined frequency;

a free running counter clocked by the clock signals and providing a count output that is incremented at the predetermined frequency;

means for addressing the memory locations in the memory by the count output of the counter, the memory providing a control signal in response to a stored digital signal at the addressed memory location;

means for generating a reference signal at a reference angular position of the engine;

means responsive to the generation of the reference signal for (A) sampling the count output of the counter, the sampled count output representing the time of occurrence T₀ of the reference pulse, (B) determining a desired delay from the time T₀ in terms of clock signals generated by the clock means for energizing the fuel injector, (C) summing the determined delay with the sampled count to determine a memory location to be addressed by the count output of the counter at a time T₁ spaced from the time T₀ by the desired delay, (D) storing a first digital signal in the memory at the determined memory location to be addressed at the time T₁, (E) determining a desired injection duration in terms of clock signals generated by the clock means, (F) summing the desired injection duration with the sum of the determined delay and the sampled count to determine a memory location to be addressed by the count output of the counter at a time T₂ spaced from the time T₁ by the desired injection duration, and (G) storing a second digital signal in the memory at the determined memory to be addressed at the time T₂, the memory providing control signals at the times T₁ and T₂ in response to the first and second digital signals stored therein, and

injector driver means (A) responsive to the control signal provided by the memory at the time T₁ for energizing the fuel injector and (B) responsive to the control signal provided by the memory at the time T₂ for deenergizing the fuel injector.