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Circuit configuration and a method of testing storage cells

  • US 4,956,819 A
  • Filed: 03/16/1988
  • Issued: 09/11/1990
  • Est. Priority Date: 03/16/1987
  • Status: Expired due to Fees
First Claim
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1. A circuit configuration for testing storage cells of anintegrated semiconductor memory which includes a block in which the storage cells are disposed in the form of a matrix, word lines and internal bit lines for driving the storage cells, evaluator circuits each being assigned to a respective internal bit line, each internal bit line having first and second mutually complementary bit line halves, a pair of first and second external bit lines, transfer transistors connecting the first external bit line to each of the first internal bit line halves and connecting the second external bit line to each of the second internal bit line halves, and a bit line decoder assigned to the respective internal bit lines and connected to gates of the transfer transistors;

  • the circuit configuration comprising a precharge device connected to said pair of external bit lines for precharging the pair of external bit lines to two mutually-complementary logic levels in a test mode, a discriminator circuit having means for sensing potentials, being connected to the pair of external bit lines and having an output for generating a fault signal indicating the occurrence of faults in test operation, the gates of all of the transfer transistors carrying a control potential, said fault signal being generated when the external bit line precharged to the higher level falls in level to at least a value which corresponds to the magnitude of a control potential on the gates of the transfer transistors minus a threshold voltage of the transfer transistors when data is read out from the memory cells during a test mode.

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