Diagnostic system for a watchdog timer

• US 4,956,842 A
• Filed: 11/16/1988
• Issued: 09/11/1990
• Est. Priority Date: 11/16/1988
• Status: Expired due to Fees

• Current Assignee: Sundstrand Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Sundstrand Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Said, Waleed
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Beausoliel, Robert W.
• Application Number:
  US07/272,059
• Time in Patent Office: 664 Days
• Field of Search: 371/16.3, 371/62, 371/3, 371/12, 364/200 MS File, 364/900 MS File
• US Class Current: 714/815
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits

Abstract

A system (10) is disclosed for testing a watchdog timer (22). The watchdog timer is associated with a system (14) which is controlled by a control program executed by a programmed processor (20) and which is monitored by a supervisory system (18) in which the watchdog timer generates an interruption signal (NMI) which interrupts the control program when the watchdog timer does not generate a reset signal within a time window measured from a last reset signal. The supervisory system contains a circuit coupled to the watchdog timer for initiating testing of the watchdog timer. The watchdog timer contains a circuit for disabling the generation of the interruption signal during testing of the watchdog timer. Furthermore, the watchdog timer contains a circuit for shutting down the system which is controlled by the control program when the control program does not resume normal operation in response to an interruption signal. The watchdog timer has a circuit for disabling the circuit for shutting down the system which is controlled by the control program during testing of the watchdog timer.

Claims

1. A testing system for a watchdog timer monitoring a programmed processor and associated with a system which is controlled by a control program executed by the programmed processor and which is monitored by a supervisory system with the watchdog timer generating an interruption signal which interrupts execution of the control program when the watchdog timer does not generate a reset comprising:

means contained in the supervisory system coupled to the watchdog timer for initiating testing of the watchdog timer; and

means contained in the watchdog timer for disabling the generation of the interruption signal during testing of the watchdog timer.

2. A testing system for a watchdog timer in accordance with claim 1 further comprising:

means coupling the watchdog timer to the supervisory system for transmitting a signal representing results of the testing of the watchdog timer to the supervisory system.

4. A testing system for a watchdog timer in accordance with claim 2 further comprising:

means coupling the watchdog timer to the supervisory system for transmitting a signal representing results of the testing of the watchdog timer to the supervisory system.

5. A testing system for a watchdog time in accordance with claim 4 wherein the watchdog timer comprises:

a decoder, coupled to the programmed processor, for decoding words transmitted from the programmed processor which generates a reset of the watchdog timer in response to decoding a predetermined sequence of words and which is coupled to the means for transmitting a signal to the supervisory system in response to decoding the predetermined sequence of words.

6. A testing system for a watchdog timer in accordance with claim 5 further comprising:

a reset latch, responsive to a clock signal received from the programmed processor and a data input of a signal indicating that the predetermined sequence of words has been received, for generating the reset in response to a simultaneous occurrence of the clock signal and the signal indicating that the predetermined sequence of words has been received.

7. A testing system for a watchdog timer in accordance with claim 6 wherein the decoder comprises:

a plurality of gates equal in number to a number of words which are contained in the predetermined sequence with each gate having a plurality of inputs coupled to the programmed processor for respectively receiving bits contained in each word;

a plurality of latches equal in number to the number of the gates for respectively receiving bits contained in each word, each latch respectively having an input causing any data of a first level which is present on a data input to be latched and an input coupled to the reset generated by the reset latch, each latch having an output with the outputs being coupled to a gate which produces an output signal of a first level in response to outputs from the latches of a first level being simultaneously present, a data input of a first latch of the plurality of latches being coupled to a constant level signal with the output of the first latch being coupled to a data input of a first latch of a group of at least one latch of the plurality of latches with the output of each of the group of latches being coupled to a data input of another of the group of latches except for a last latch within the group which does not have a data output coupled to a data input of a latch in the group of latches;

a first gate having a pair of inputs with the first input being coupled to the output of the gate which produces the output signal of a first level and a second input being coupled to a signal indicating that the watchdog timer is being tested, the first gate producing an output signal which is the data input of the latch generating the reset signal with the first gate producing a data signal of a first level in response to the signal indicating that the watchdog timer is being tested is not present and the predetermined sequence of words is present;

a second gate having a pair of inputs with the first input of the second gate being coupled to the output of the gate which produces an output signal of a predetermined level and the second input of the second gate being coupled to the signal indicating that the watchdog timer is being tested and producing an output signal of a first level when both of the inputs have an identical predetermined level; and

a test result storing latch having a constant level data input and an input of the output of the second gate for producing an output identical to the data input in response to the output signal of the second gate being the first level and a clear input coupled to the signal indicating that the watchdog timer is being tested for resetting the test result storing latch at an end of the signal indicating that the watchdog timer is being tested, the output of the test result storing latch being coupled to the means for transmitting.

8. A testing system for a watchdog timer in accordance with claim 4 further comprising:

means, responsive to a means for generating the interruption signal, for providing a signal to the means coupling the watchdog timer to the supervisory system to signal the supervisory system of the generation of an interruption signal and signalling the supervisory system if a malfunction exists during testing of the means for generating the interruption signal and disabling the means for generating the interruption signal during testing.

3. A testing system for a watchdog timer monitoring a programmed processor and associated with a system which is controlled by a control program executed by the programmed processor and which is monitored by a supervisory system with the watchdog timer generating an interruption signal which interrupts execution of the control program when the watchdog timer does not generate a reset comprising:

means contained in the supervisory system coupled to the watchdog timer for initiating testing of the watchdog timer; and

means contained in the watchdog timer for disabling the generation of the interruption signal during testing of the watchdog timer;

wherein the watchdog timer further comprises;

means for shutting down the system which is controlled by the control program when the control program does not resume normal operation in response to an interruption signal; and

wherein

the watchdog timer has means for disabling the means for shutting down the system which is controlled by the control program during testing of the watchdog timer.

9. A testing system for a watchdog timer monitoring a programmed processor and associated with a system which is controlled by a control program executed by the programmed processor and which is monitored by a supervisory system with the watchdog timer generating an interruption signal which interrupts execution of the control program when the watchdog timer does not generate a reset comprising:

means contained in the supervisory system coupled to the watchdog timer for initiating testing of the watchdog timer;

means contained in the watchdog timer for disabling the generation of the interruption signal during testing of the watchdog timer; and

means coupling the watchdog timer to the supervisory system for transmitting a signal representing results of the testing of the watchdog timer to the supervisory system;

wherein the watchdog timer comprises a decoder, coupled to the programmed processor, for decoding words transmitted from the programmed processor which generates a reset of the watchdog timer in response to decoding a predetermined sequence of words and which is coupled to the means for transmitting a signal to the supervisory system in response to decoding the predetermined sequence of words.

10. A testing system for a watchdog timer in accordance with claim 9 further comprising:

a reset latch, responsive to a clock signal received from the programmed processor and a data input of a signal indicating that the predetermined sequence of words has been received, for generating the reset in response to a simultaneous occurrence of the clock signal and the signal indicating that the predetermined sequence of words has been received.

11. A testing system in accordance with claim 10 wherein the decoder comprises:

a plurality of gates equal in number to a number of words which are contained in the predetermined sequence with each gate having a plurality of inputs coupled to the programmed processor for respectively receiving bits contained in each word;

a plurality of latches equal in number to the number of the gates for respectively receiving bits contained in each word, each latch respectively having an input causing any data of a first level which is present on a data input to be latched and an input coupled to the reset generated by the reset latch, each latch having an output with the outputs being coupled to a gate which produces an output signal of a first level in response to outputs from the latches of a first level being simultaneously present, a data input of a first latch of the plurality of latches being coupled to a constant level signal with the output of the first latch being coupled to a data input of a first latch of a group of at least one latch of the plurality of latches with the output of each of the group of latches being coupled to a data input of another of the group of latches except for a last latch within the group which does not have a data output coupled to a data input of a latch in the group of latches;

a first gate having a pair of inputs with the first input being coupled to the output of the gate which produces the output signal of a first level and a second input being coupled to a signal indicating that the watchdog timer is being tested, the first gate producing an output signal which is the data input of the latch generating the reset signal with the first gate producing a data signal of a first level in response to the signal indicating that the watchdog timer is being tested is not present and the predetermined sequence of words is present;

a second gate having a pair of inputs with the first input of the second gate being coupled to the output of the gate which produces an output signal of a predetermined level and the second input of the second gate being coupled to the signal indicating that the watchdog timer is being tested and producing an output signal of a first level when both of the inputs have an identical predetermined level; and

a test result storing latch having a constant high level data input and an input of the output of the second gate for producing an output identical to the data input in response to the output signal of the second gate being the first level and a clear input coupled to the signal indicating that the watchdog timer is being tested for resetting the test result storing latch at an end of the signal indicating that the watchdog timer is being tested, the output of the test result storing latch being coupled to the means for transmitting.

12. A testing system for a watchdog timer in accordance with claim 9 further comprising:

means, coupled to the decoder, for controlling the interruption of the control program with the interruption signal being produced when a reset signal is not produced inside a time window measured with respect to a previous reset pulse.

13. A testing system for a watchdog timer in accordance with claim 12 further comprising:

means, coupled to the means for transmitting, for signalling the supervisory system when a reset pulse is generated before the time window; and

means, responsive to the means for initiating testing, for disabling the means for signalling the supervisory system when a reset pulse is generated before the time window and signalling the supervisory system if a malfunction exists during testing of the means for signalling the supervisory system when a reset pulse is generated before the time window.

14. A testing system for a watchdog timer in accordance with claim 13 wherein the means for disabling and signalling comprises:

a time window gate having a pair of inputs and an output, the first input having a first level in response to a reset pulse being produced before the time window and a second level in response to a reset not occurring before the time window, the second input being a first level in response to a reset not occurring by an end of the time window, the output being a first level when either a reset occurs before the time window or not occurring by an end of the time window.

15. A testing system, for a watchdog timer in accordance with claim 12 comprising:

means, coupled to the means for transmitting, for signalling the supervisory system when a reset pulse is generated after the time window; and

means, responsive to the means for initiating testing, for disabling the means for signalling the supervisory system when a reset pulse is generated after the time window and signalling the supervisory system if a malfunction exists during testing of the means for signalling the supervisory system when a reset pulse is generated after the time window.

16. A testing system for a watchdog timer in accordance with claim 15 wherein the means for disabling and signalling comprises:

a time window gate having a pair of inputs and an output, the first input having a first level in response to a reset pulse being produced before the time window and a second level in response to a reset not occurring before the time window, the second input being a first level in response to a reset not occurring by an end of the time window, the output being a first level when either a reset occurs before the time window or not occurring by an end of the time window.

17. A testing system for a watchdog timer in accordance with claim 9 further comprising:

means, coupled to the means for transmitting, for signalling the supervisory system when a reset pulse is generated before the time window;

means, responsive to the means for initiating testing, for disabling the means for signalling the supervisory system when a reset pulse is generated before the time window and signalling the supervisory system if a malfunction exists during testing of the means for signalling the supervisory system when a reset pulse is generated before the time window;

means, coupled to the means for transmitting, for signalling the supervisory system when a reset pulse is generated after the time window; and

means, responsive to the means for initiating testing, for disabling the means for signalling the supervisory system when a reset pulse is generated after the time window and signalling the supervisory system if a malfunction exists during testing of the means for signalling the supervisory system when a reset pulse is generated after the time window.

18. A testing system for a watchdog timer in accordance with claim 17 further comprising:

a time window gate having a pair of inputs and an output, the first input having a first level in response to a reset pulse being produced before the time window and a second level in response to a reset not occurring before the time window, the second input being a first level in response to a reset not occurring by an end of the time window, the output being a first level when either a reset occurs before the time window or not occurring by an end of the time window.

19. A testing system for a watchdog timer monitoring a programmed processor and associated with a system which is controlled by a control program executed by the programmed processor and which is monitored by a supervisory system with the watchdog timer generating an interruption signal which interrupts execution of the control program when the watchdog timer does not generate a reset comprising:

means contained in the supervisory system coupled to the watchdog timer for initiating testing of the watchdog timer; and

means contained in the watchdog timer for disabling the generation of the interruption signal during testing of the watchdog timer;

wherein the system which is controlled by the control program is an electrical power generator in an airframe.

20. A testing system for a watchdog timer in accordance with claim 19 wherein:

the supervisory system is a bus control unit.

21. A testing system for a watchdog timer which monitors the operation of a programmed processor with the watchdog timer having means for generating an interruption signal to interrupt execution of a program by the programmed processor comprising:

means, coupled to the watchdog timer, for initiating testing of the watchdog timer; and

means for disabling generation of the interruption signal by the means for generating the interruption signal during testing of the watchdog timer.

22. A testing system for a watchdog timer which monitors the operation of a programmed processor with the watchdog timer having means for generating an interruption signal to interrupt execution of a program by the programmed processor comprising:

means, coupled to the watchdog timer, for initiating testing of the watchdog timer;

means for disabling generation of the interruption signal by the means for generating the interruption signal during testing of the watchdog timer;

a system which is controlled by the program executed by the programmed processor; and

means for shutting down the system which is controlled by the program when the program does not resume normal operation in response to an interruption signal;

wherein;

the watchdog timer has means for disabling the means for shutting down the system which is controlled by the program during testing of the watchdog timer.

23. In a system including a watchdog timer and a programmed processor, a method of monitoring the programmed processor comprising the steps:

transmitting a signal from the programmed processor to the watchdog timer;

generating an interruption signal in the watchdog timer when the transmitted signal indicates that the programmed processor is not operating normally, said interruption signal interrupting execution of a program by the programmed processor;

initiating testing of the watchdog timer; and

disabling generation of the interruption signal by the watchdog timer during the testing of the watchdog timer so that during the testing the watchdog timer does not generate an interruption signal even if the transmitted signal indicates that the programmed processor is not operating normally.

24. A method of monitoring a programmed processor according to claim 23, further comprising the steps:

shutting down a system which is controlled by the program executed by the programmed processor when the program does not resume normal operation in response to the interruption signal; and

disabling the shutting down of the system which is controlled by the program during the testing of the watchdog timer.