Integrated circuit device having row structure with clock driver at end of each row

• US 4,958,092 A
• Filed: 03/28/1989
• Issued: 09/18/1990
• Est. Priority Date: 03/29/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Shigeru
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): RUBIN, MARGARET R
• Application Number:
  US07/329,908
• Time in Patent Office: 539 Days
• Field of Search: 307/480, 307/303, 307/303.1, 307/5, 307/443, 307/269
• US Class Current: 327/297
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

In an integrated circuit device such as a logic LSI having a row structure, each row includes a group of logic elements and a clock driver. The clock driver in each row is arranged at one end of the row so as to shorten the distances from the clock driver to a primary power supply wiring and a primary ground wiring.

Claims

1. An integrated circuit device comprising:

a primary power supply wiring connected to a power supply;

a primary ground wiring connected to a ground terminal, for holding a reference potential;

primary clock driver means, for receiving a clock signal from a clock signal input terminal;

a first clock signal input wiring for connecting said clock signal input terminal to said primary clock driver means;

a first row including a first secondary clock driver arranged at one end of said first row to be adjacent to a primary power supply wiring and a primary ground wiring, said first secondary clock driver having a clock signal input terminal connected to said primary clock driver means, a power supply terminal connected to said primary power supply wiring, and a ground terminal connected to said primary ground wiring, and a first group of a plurality of logic elements, which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said primary power supply wiring and said primary ground wiring;

a first secondary power supply wiring for connecting said primary power supply wiring to said power supply terminal of said first secondary clock driver in said first row, and to said power supply terminals of said first group of logic elements;

a first secondary ground wiring for connecting said primary ground wiring to said ground terminal of said first secondary clock driver in said first row, and to said ground terminals of said logic elements;

a second row arranged parallel to a longitudinal direction of said first row, said second row including a second secondary clock driver arranged at one end of said second row to be adjacent to said primary power supply wiring and said primary ground wiring, said second secondary clock driver having a clock signal input terminal connected to said primary clock driver means, a power supply terminal connected to said primary power supply wiring, and a ground terminal connected to said primary ground wiring, and a second group of a plurality logic elements, which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said primary power supply wiring and said primary ground wiring;

a second secondary power supply wiring for connecting said primary power supply wiring to said power supply terminal of said second secondary clock driver in said second row, and to said power supply terminals of said second group of logic elements;

a second secondary ground wiring for connecting said primary ground wiring to said ground terminal of said second secondary clock driver in said second row and to said ground terminals of said logic elements;

a second clock signal input wiring for connecting the input terminals of said first and second secondary clock drivers and to an output terminal of said primary clock driver means;

a first clock signal wiring for connecting said first secondary clock driver means in said first row to said logic elements; and

a second clock signal wiring for connecting said second secondary clock driver means in said second row to said logic elements.

2. A device according to claim 1, wherein said primary power supply wiring, said primary ground wiring, and said second clock signal input wiring are arranged in a direction perpendicular to the longitudinal direction of said first and second rows, and arranged on said first and second secondary clock drivers corresponding to said first and second rows.

3. A device according to claim 1, comprising:

first and second primary power supply wirings commonly connected to said power supply, and divided to be arranged as two lines;

first and second primary ground wirings commonly connected to said ground terminal, and divided to be arranged as two lines, for holding a reference potential;

primary clock driver means, for receiving the clock signal from said clock signal input terminal;

a first clock signal input wiring for connecting said clock signal input terminal to said primary clock driver means;

a first row including first and second secondary clock drivers, said drivers respectively having clock signal input terminals connected to said primary clock driver means, power supply terminals respectively connected to said first and second primary power supply wirings, and ground terminals respectively connected to said first and second primary ground wirings, a first group of a plurality of logic elements, which switch synchronously with the input clock signal, each having power supply terminals and ground terminals respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings;

a first secondary power supply wiring for respectively connecting said first and second primary power supply wirings to said power supply terminals of said first and second secondary clock drivers in said first row, and to said power supply terminals of said first group of logic elements;

a first secondary ground wiring for respectively connecting said first and second primary ground wirings to said ground terminals of said first and second secondary clock drivers in said first row, and to said ground terminals of said first group of logic elements;

a second row arranged parallel to the longitudinal direction of said first row, said second row including first and second secondary clock drivers, said drivers respectively having clock signal input terminals connected to said primary clock driver means, power supply terminals connected to said first and second primary power supply wirings, and ground terminals connected to said first and second primary ground wirings, and a second group of a plurality of logic elements, which switch synchronously with the input clock signal, each having power supply terminals and ground terminals respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings;

a second secondary power supply wiring for connecting said first and second primary power supply wirings to said power supply terminals of said first and second secondary clock drivers in said second row and to said power supply terminals of said second group of logic elements;

a second secondary ground wiring for respectively connecting said first and second primary ground wirings to said ground terminals of said first and second secondary clock drivers in said second row, and to said ground terminals of said second group of logic elements;

secondary clock signal input wirings divided from an output terminal of said primary clock driver means, and respectively connected to said first secondary clock drivers, and to said second secondary clock drivers, respectively, included in said first and second rows;

a first clock signal wiring for commonly connecting said first secondary clock driver in said first row to logic elements corresponding to said first and second rows and included therein; and

a second clock signal wiring for commonly connecting said second secondary clock driver in said first row to said logic elements corresponding to said first and second rows and included therein.

4. A device according to claim 3, wherein said first and second primary power supply wirings, said first and second primary ground wirings, and said secondary clock signal input wirings are arranged in a direction perpendicular to the longitudinal direction of said first and second rows, and arranged on said first and second secondary clock drivers.