Queued serial peripheral interface for use in a data processing system

• US 4,958,277 A
• Filed: 04/21/1989
• Issued: 09/18/1990
• Est. Priority Date: 07/24/1987
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hill, Susan C., DeBrito, Daniel N., Jelemensky, Joseph, Heene, Mark R., Groves, Stanley E.
• Primary Examiner(s): Eng, David Y.
• Assistant Examiner(s): Harrell, Robert B.
• Application Number:
  US07/342,651
• Time in Patent Office: 515 Days
• Field of Search: 364/200, 364/900, 364/300
• US Class Current: 710/52
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A serial peripheral interface achieves compatibility with devices having previous such interfaces while singificantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.

Claims

1. A microcomputer comprising a central processing unit and a serial data communication apparatus, the serial data communication apparatus further comprising:

a first memory coupled to the central processing unit, said first memory having a first predetermined number of storage locations;

transfer means coupled to said first memory for executing serial data transfers between the serial data communication apparatus and at least one other device coupled thereto, the transfer means further comprising;

means for retrieving data from said first memory at a first one of said first predetermined number of storage locations;

means for transmitting said retrieved data to said at least one other device;

means for receiving data from said at least one other device; and

means for storing said received data in said first memory at a second one of said first predetermined number of storage locations;

a second memory coupled to the central processing unit, said second memory having a second predetermined number of storage locations;

queue pointer means coupled to said first memory means for maintaining a queue pointer value which specifies said first one of said first predetermined number of storage locations; and

control means coupled to said central processing unit, said transfer means, said first and second memories and said queue pointer means for responding to a first state of an enable bit stored in said second memory at a first one of said second predetermined number of storage locations by directing said transfer means to execute one of said serial data transfers and by incrementing said queue pointer value and for responding to a second state of said enable bit by disabling said transfer means;

the serial data communication apparatus is characterized in that;

said control means is further responsive to the central processing unit, while said enable bit is in said first state, to modify said queue pointer value by replacing said queue pointer value with a new queue pointer value provided by the central processing unit instead of incrementing said queue pointer value.

2. A microcomputer according to claim 1 wherein the serial data communication apparatus is further characterized in that:

said queue pointer value also specifies said second one of said first predetermined number of storage locations.

3. A microcomputer according to claim 1 wherein the serial data communication apparatus further comprises:

select means coupled to said control means for retrieving data from said first memory at a third one of said first predetermined number of storage locations and for selecting one of said at least one other device in accordance with said retrieved data;

the serial data communication apparatus is further characterized in that;

said queue pointer value also specifies said third one of said first predetermined number of storage locations.

4. A microcomputer according to claim 1 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a first state of a continue bit stored in said first memory at a fourth one of said first predetermined number of storage locations by directing said select means to become inactive while said queue pointer value is being incremented and is responsive to a second state of said continue bit by directing said select means to remain active while said queue pointer value is being incremented; and

said queue pointer value also specifies said fourth one of said first predetermined number of storage locations.

5. A microcomputer according to claim 1 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a value of an end queue pointer bit field stored in said second memory at a second one of said second predetermined number of locations by disabling said transfer means.

6. A microcomputer according to claim 5 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a first state of a wrap bit stored in said second memory at a third one of said second predetermined number of locations by setting said queue point value to a predetermined value instead of disabling said transfer means.

7. A microcomputer comprising a central processing unit and a serial data communication apparatus, the serial data communication apparatus further comprising:

a first memory coupled to the central processing unit, said first memory having a first predetermined number of storage locations;

transfer means coupled to said first memory for executing serial data transfers between the serial data communication apparatus and at least one other device coupled thereto, the transfer means further comprising;

means for retrieving data from said first memory at a first one of said first predetermined number of storage locations;

means for transmitting said retrieved data to said at least one other device;

means for receiving data from said at least one other device; and

means for storing said received data in said first memory at a second one of said first predetermined number of storage locations;

a second memory coupled to the central processing unit, said second memory having a second predetermined number of storage locations;

queue pointer means coupled to said first memory means for maintaining a queue pointer value which specifies said first one of said first predetermined number of storage locations;

control means coupled to said central processing unit, said transfer means, said first and second memories and said queue pointer means for responding to a first state of an enable bit stored in said second memory at a first one of said second predetermined number of storage locations by directing said transfer means to execute one of said serial data transfers and by incrementing said queue pointer value and for responding to a second state of said enable bit by disabling said transfer means; and

select means coupled to said control means for retrieving data from said first memory at a third one of said first predetermined number of storage locations and for selecting one of said at least one other device in accordance with said retrieved data;

the serial data communication apparatus is characterized in that;

said queue pointer value also specifies said third one of said first predetermined number of storage locations.

8. A microcomputer according to claim 7 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a first state of a continue bit stored in said first memory at a fourth one of said first predetermined number of storage locations by directing said select means to become inactive while said queue pointer value is being incremented and is responsive to a second state of said continue bit by directing said select means to remain active while said queue pointer value is being incremented; and

said queue pointer value also specifies said fourth one of said first predetermined number of storage locations.

9. A microcomputer according to claim 8 wherein the serial data communication apparatus is further characterized in that:

said queue pointer value also specifies said second one of said first predetermined number of storage locations.

10. A microcomputer according to claim 9 wherein the serial data communication apparatus further comprises:

the serial data communication apparatus is further characterized in that;

said control means is further responsive to the central processing unit, while said enable bit is in said first state, to modify said queue pointer value by replacing said queue pointer value with a new queue pointer value provided by the central processing unit instead of incrementing said queue pointer value.

11. A microcomputer according to claim 7 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a value of an end queue pointer bit field stored in said second memory at a second one of said second predetermined number of locations by disabling said transfer means.

12. A microcomputer according to claim 11 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a first state of a wrap bit stored in said second memory at a third one of said second predetermined number of locations by setting said queue pointer value to a predetermined value instead of disabling said transfer means.

13. A microcomputer comprising a central processing unit and a serial data communication apparatus, the serial data communication apparatus further comprising:

a first memory coupled to the central processing unit, said first memory having a first predetermined number of storage locations;

transfer means coupled to said first memory for executing serial data transfers between the serial data communication apparatus and at least one other device coupled thereto, the transfer means further comprising;

means for retrieving data from said first memory at a first one of said first predetermined number of storage locations;

means for transmitting said retrieved data to said at least one other device;

means for receiving data from said at least one other device; and

means for storing said received data in said first memory at a second one of said first predetermined number of storage locations;

a second memory coupled to the central processing unit, said second memory having a second predetermined number of storage locations;

queue pointer means coupled to said first memory means for maintaining a queue pointer value which specifies said first one of said first predetermined number of storage locations; and

control means coupled to said central processing unit said transfer means, said first and second memories and said queue pointer means for responding to a first state of an enable bit stored in said second memory at a first one of said second predetermined number of storage locations by directing said transfer means to execute one of said serial data transfers and by incrementing said queue pointer value and for responding to a second state of said enable bit by disabling said transfer means;

the serial data communication apparatus is characterized in that;

said control means is further responsive to a value of an end queue pointer bit field stored in said second memory at a second one of said second predetermined number of locations by disabling said transfer means.

14. A microcomputer according to claim 13 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a first state of a wrap bit stored in said second memory at a third one of said second predetermined number of locations by setting said queue pointer value to a predetermined value instead of disabling said transfer means.

15. A microcomputer according to claim 14 wherein the serial data communication apparatus is further characterized in that:

said queue pointer value also specifies said second one of said first predetermined number of storage locations.

16. A microcomputer according to claim 15 wherein the serial data communication apparatus further comprises:

select means coupled to said control means for retrieving data from said first memory at a third one of said first predetermined number of storage locations and for selecting one of said at least one other device in accordance with said retrieved data;

the serial data communication apparatus is further characterized in that;

said queue pointer value also specifies said third one of said first predetermined number of storage locations.

17. A microcomputer according to claim 16 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to a first state of a continue bit stored in said first memory at a fourth one of said first predetermined number of storage locations by directing said select means to become inactive while said queue pointer value is being incremented and is responsive to a second state of said continue bit by directing said select means to remain active while said queue pointer value is being incremented; and

said queue pointer value also specifies said fourth one of said first predetermined number of storage locations.

18. A microcomputer according to claim 17 wherein the serial data communication apparatus is further characterized in that:

said control means is further responsive to the central processing unit, while said enable bit is in said first state, to modify said queue pointer value by replacing said queue pointer value with a new queue pointer value provided by the central processing unit instead of incrementing said queue pointer value.