Apparatus for exchanging pixel data among pixel processors

• US 4,958,303 A
• Filed: 05/12/1988
• Issued: 09/18/1990
• Est. Priority Date: 05/12/1988
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Walton, Lea, Assarpour, Hamid
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Zimmerman, Mark K.
• Application Number:
  US07/193,923
• Time in Patent Office: 859 Days
• Field of Search: 364/521, 364/518, 364/200 MS File, 364/900 MS File
• US Class Current: 345/505
• CPC Class Codes: G06T 17/00 Three dimensional [3D] modelling, e.g. data description of 3D objects
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

Computer graphics apparatus including a host computer, a plurality of pixel-processors and associated respective frame buffers controlled by the host computer to permit simultaneous pixel-processing, a device for displaying a graphics image described by pixel data stored in the frame buffers, and switching circuitry connected for simultaneously receiving pixel data from source pixel-processors and returning the pixel data to selected destination pixel-processors.

Claims

1. Computer graphics apparatus comprising

a host computer,

a plurality of pixel-processors and frame buffers, said frames buffers being connected to communicate with respective pixel-processors, said pixel-processors and frame buffers being controlled by said host computer to permit simultaneous pixel-processing,

means for displaying a graphics image described by pixel data stored in said frame buffers, said means being connected to receive said pixel data, and

first switching circuitry for simultaneously receiving pixel data from each said pixel-processor and returning said pixel data from each pixel-processor to a selected one of said plurality of pixel-processors,

said first switching circuitry including a plurality of inputs and outputs, each said input being connected to a respective pixel processor to receive pixel data from it, each said output being connected to a respective pixel processor to return pixel data to it, said circuitry including electrical connections and switches therein permitting selective connection of any said input to any said output.

2. The apparatus of claim 1 wherein

said pixel data correspond to pixels arranged in rows and columns in cells,

said pixel-processors are arranged in rows and columns, each said pixel-processor processing pixels at a particular row and column position for all said cells, and

said first switching circuitry includes a column multiplexing stage of column multiplexers for controlling the column positions of said pixel data returned to said pixel processors and a row multiplexing stage of row multiplexers for controlling the row positions of said pixel data returned to said pixel processors, the outputs of one said stage providing the inputs for the other said stage.

3. The apparatus of claim 1 further comprising second switching circuitry for simultaneously receiving pixel data from said pixel processors and returning said pixel data to selected different said pixel processors,

said second switching circuitry being connected in parallel to said first switching circuitry so as to provide increased speed of transfer.

4. The apparatus of claim 3 wherein each said first and second switching circuitry includes a column multiplexing stage of column multiplexers for controlling the column positions of said pixel data returned to said pixel processors and a row multiplexing stage of row multiplexers for controlling the row positions of said pixel data returned to said pixel processors, the output of one said stage providing the input for the other said stage.

6. The apparatus of claim 3 wherein said column multiplexing stage includes, for each row of pixel-processors, a column multiplexer receiving data over serial data output lines of respective pixel processors in the row of pixel-processors.

7. The apparatus of claim 6 wherein the row multiplexing stage includes, for each row of pixel-processors, a row multiplexer receiving data from all column multiplexers and returning data received from one said column multiplexer to a row of pixel-processors via serial data input lines of respective pixel processors in the row of pixel-processors.

8. The apparatus of claim 6 wherein each said column multiplexer includes N said group inputs, where N is a number of columns in said cell, and said column multiplexers have equal amounts of column shifting associated with corresponding multiplexer inputs and receive common control signals selecting which group input is provided as an output.

9. The apparatus of claim 8 wherein each said row multiplexer includes M said group inputs, where M is a number of rows in said cell, and said row multiplexers have an equal amount of row shifting associated with corresponding multiplexer inputs and receive common control signals selecting which group input is provided as an output.

5. A computer graphics apparatus comprising

a host computer,

a plurality of pixel-processors and frame buffers, said frame buffers being connected to communicate with respective pixel-processors, said pixel-processors and frame buffers being controlled by said host computer to permit simultaneous pixel-processing,

means for displaying a graphics image described by pixel data stored in said frame buffers, said means being connected to receive said pixel data, and

first switching circuitry for simultaneously receiving pixel data from each said pixel-processor and returning said pixel data from each said pixel-processor to a selected one of said plurality of pixel-processors,

said switching circuitry including a plurality of pixel processor inputs and outputs, each said input being connected to a respective pixel processor to receive data from it, each said output being connected to a respective pixel processor to return pixel data to it,

said pixel data corresponding to pixels arranged in rows and columns in cells,

said pixel-processors being arranged in rows and columns, each said pixel-processor processing pixels at a particular row and column position for all said cells,

said first switching circuitry including a column multiplexing stage of column multiplexers for controlling the column positions of said pixel data returned to said pixel processors and a row multiplexing stage of row multiplexers for controlling the row positions of said pixel data returned to said pixel processors, the outputs of one stage providing the inputs for the other said stage,

each said pixel processor input being connected to a plurality of group inputs to said multiplexers, each said group input including a plurality of pixel processor inputs, said pixel processor inputs making up a group input being in different orders with respect to other pixel processor inputs in different group inputs provided to a multiplexer, said different orders including different row or column rotations of said pixel processor inputs, a said multiplexer providing one said group input as an output.

10. Computer graphics apparatus comprising

a host computer,

a plurality of pixel-processors and frame buffers, said frame buffers being connected to communicate with respective pixel-processors, said pixel-processors and frame buffers being controlled by said host computer to permit simultaneous pixel-processing,

means for displaying a graphics image described by pixel data stored in said frame buffers, said means being connected to receive said pixel data,

first switching circuitry for simultaneously receiving pixel data from each said pixel-processor and returning said pixel data from each pixel-processor to a selected one of said plurality of pixel-processors, and

second switching circuitry for simultaneously receiving pixel data from each said pixel-processor and returning said pixel data from each pixel-processor to a selected one of said plurality of pixel-processors,

each said first and second switching circuitry including a column multiplexing stage of column multiplexers for controlling the column positions of said pixel data returned to said pixel processors and a row multiplexing stage of row multiplexers for controlling the row positions of said pixel data returned to said pixel processors, the output of one said stage providing the input for the other said stage,

said switching circuitry including a plurality of pixel processor inputs and outputs, each said input being connected to a respective pixel processor to receive data from it, each said output being connected to a respective pixel processor to return pixel data to it,

each said pixel processor input being connected to a plurality of group inputs to said multiplexers, each said group input including a plurality pixel processor inputs, said pixel processor inputs being in different orders with respect to other pixel processor inputs in different group inputs provided to a multiplexer, said different orders including different row or column rotations of said pixel processor inputs, a said multiplexer providing one said group input as an output,

said second switching circuitry being connected in parallel to said first switching circuitry so as to provide increased speed of transfer.

11. The apparatus of claim 11 wherein each said column multiplexing stage includes, for each row of pixel-processors, a column multiplexer receiving data over serial data output lines of respective pixel processors in the row of pixel-processors.

12. The apparatus of claim 11 wherein each said row multiplexing stage includes, for each row of pixel-processors, a row multiplexer receiving data from all column multiplexers and returning data received from one said column multiplexer to a row of pixel-processors via serial data input lines of respective pixel processors in the row of pixel-processors.

13. The apparatus of claim 7 or 12 further comprising means for providing column rotation control signals and row rotation control signals, said column rotation control signals being provided to all multiplexers of said stage of column multiplexers and said row rotation control signals being provided to all multiplexers of said stage of row multiplexers.

14. A method of swapping pixel data among a plurality of frame buffers in a computer graphics system having an arrangement of a plurality of pixel-processors with associated frame buffers comprising

providing switching circuitry connected to receive data from and return data to said pixel-processors, and

simultaneously receiving pixel data from each said pixel-processor at said switching circuitry and returning said pixel data to a selected one of said plurality of pixel-processors,

said first switching circuitry including a plurality of inputs and outputs, each said input being connected to a respective pixel processor to receive pixel data from it, each said output being connected to a respective pixel processor to return pixel data to it, said circuitry including electrical connections and switches therein permitting selective connection of any said input to any said output.

15. Circuitry for swapping pixel data among a plurality of frame buffers in a computer graphics system including a host computer, and a display means, and an arrangement of a plurality of pixel-processors with associated frame buffers, said circuitry comprising,

receiving means for receiving pixel data from said pixel-processors, said receiving means including a plurality of inputs that are each connected to a respective pixel processor to receive pixel data from it, and

returning means connected to said receiving means for returning said pixel data from each said pixel processor to a selected one of said plurality of pixel-processors simultaneously with the receiving of said pixel data by said receiving means,

said returning means including a plurality of outputs that are each connected to a respective pixel processor to return pixel data to it, said receiving means and said returning means including electrical connections and switches permitting selective connection of any said input with any said output.

16. The circuitry of claim 15 wherein said pixel data correspond to pixels arranged in rows and columns in cells, each said pixel-processor processing pixels at a respective row and column position in said cells, and

wherein said receiving means includes a column multiplexing stage of columns multiplexers for controlling the column positions of said pixel data transmitted to a row multiplexing stage and thereafter returned to said pixel processors, and said returning means includes said row multiplexing stage of row multiplexing for controlling the row positions of said pixel data returned to said pixel processors.

17. Circuitry for swapping pixel data among a plurality of frame buffers in a computer graphics system including a host computer and a display means and having an arrangement of a plurality of pixel-processors with associated frame buffers, said circuitry comprising,

receiving means for receiving pixel data from said pixel-processors,

said pixel data corresponding to pixels arranged in rows and columns in cells, each said pixel-processor processing pixels at a particular row and column position in said cells,

returning means connected to said receiving means for returning said pixel data from each said pixel processor to a selected one of said plurality of pixel-processors simultaneously with the receiving of said pixel data by said receiving means,

said receiving means including a column multiplexing stage of column multiplexers for controlling the column positions of said pixel data transmitted to a row multiplexing stage and thereafter returned to said pixel processors, and said returning means including said row multiplexing stage of row multiplexers for controlling the row positions of said pixel data returned to said pixel processors, and

said switching circuitry including a plurality of pixel processor inputs and outputs, each said input being connected to a respective pixel processor to receive data from it, each said output being connected to a respective pixel processor to return pixel data to it,

each said pixel processor input being connected to a plurality of group inputs to said multiplexers, each said group input including a plurality of pixel processor inputs, said pixel processor inputs being in different orders with respect to other pixel processor inputs in different group inputs provided to a multiplexer, said different orders including different row or column rotations of said pixel processor inputs, a said multiplexer providing one said group input as an output.

18. The circuitry of claim 17 wherein said column multiplexing stage includes, for each row of pixel-processors, a column multiplexer for receiving data over serial data output lines of respective pixel processors in the row of pixel-processors.

19. The circuitry of claim 18 wherein the row multiplexing stage includes, for each row of pixel-processors, a row multiplexer for receiving data from all column multiplexers and for returning data received from one said column multiplexer to a row of pixel-processors via serial data input lines of respective pixel processors in the row of pixel-processors.

20. The circuitry of claim 19 wherein each said column multiplexer includes N said group inputs, where N is a number of columns in said cell, and said column multiplexers have equal amounts of column shifting associated with corresponding multiplexer inputs and receive common control signals selecting which group input is provided as an output.

21. The circuitry of claim 20 wherein each said row multiplexer includes M said group inputs, where M is a number of rows in said cell, and said row multiplexers have an equal amount of row shifting associated with corresponding multiplexer inputs and receive common control signals selecting with group input is provided as an output.