Circuit for recovering the carrier in digital transmission systems

• US 4,958,360 A
• Filed: 10/11/1989
• Issued: 09/18/1990
• Est. Priority Date: 09/25/1987
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Sari, Hikmet
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US07/420,681
• Time in Patent Office: 342 Days
• Field of Search: 375/39,42, 375/81, 375/83, 375/97, 375/120, 375/102, 329/104, 329/109, 329/110, 329/112, 329/124
• US Class Current: 375/344
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0075 Error weighting
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop

Abstract

A circuit for recovering the carrier of a digitally modulated wave comprising a voltage-controlled oscillator (17) that is controlled by an error signal ε(φ) in order to adjust the phase of the oscillator, the modulated wave being introduced into two channels, the one in phase (10) and the other in quadrature (20) with the carrier, the two channels being joined together by a phase comparator arrangement (25) which produces the error signal and a sampling clock (H1). The phase comparator arrangement (25) alternately operates as a phase detector and as a frequency detector and therefore comprises an apparatus for selecting received signal points with the aid of selection zones formed by ring segments, situated around certain states of the signal constellation. The signals of the in-phase and quadrature channels are used to address a memory (26) that contains the information belonging to or not belonging to the signal point received in one of the selected zones as well as the amplitude and the error sign that relate thereto. In addition, the phase comparator arrangement (25) comprises apparaturs (28, 29) for generating the sampling clock (H1) which, in the acquisition mode (off-hook), validates the basic clock H only for these selected zones and, in the permanent mode (on-hook), validates all the edges of the clock H for forming the sampling clock.

Claims

1. A circuit for recovering a carrier from a digitally modulated wave having a phase symmetry 2π

/M, where M is an integer representing a symmetry order of a modulation scheme of said digitally modulated signal, said modulation scheme corresponding to a signal constellation having states, which states are representable using a graphic representation in polar coordinates by a function F(A,Φ

), where A and Φ

represent modulus and phase, respectively, of the states in the signal constellation, the circuit comprising;

(a) a voltage-controlled oscillator having an output for supplying an output signal which represents said carrier and a control input for receiving an error signal ε

(φ

) for changing a phase of the oscillator to adjust it to a phase of said digitally modulated wave, the phase φ

being the phase difference between signal points of received digitally modulated wave and corresponding states, idealized ones of said signal points being states of said signal constellation;

(b) a first channel for in-phase demodulation;

(c) a second channel for quadrature-phase demodulation;

(d) phase comparing means, coupled to outputs of the first and second channels and to receive a basic recovered clock signal H, for determining and validating a comparator signal, the phase comparing means alternatively operating as phase detector and as a frequency detector and comprising means for selecting received signal points using selection zones, said selection zones being defined with respect to said graphic representation as located around certain states of the signal constellation, said selection zones appearing in said graphic representation as ring segments;

(e) means for producing a variable rate sampling clock signal which reproduces the basic clock signal H by discarding certain edges, said producing means;

(i) when the circuit is in acquisition mode (unlocked), validating the basic clock signal H only for the selection zone; and

(ii) when the circuit is in permanent mode (locked), validating all edges of the clock signal H for forming the sampling clock signal;

said sampling clock signal being supplied to the comparing means to control validating of the comparator signal; and

(f) means for converting the comparator signal to the error signal ε

(φ

).

2. The circuit of claim 1 wherein each ring segment comprises an intersection of two respective regions:

(a) first, a respective angular section (-θ

,θ

) corresponding to a phase difference φ

between a signal point of the received digitally modulated wave and a corresponding state of the signal constellation, such that the absolute value of φ

is less than θ

, where θ

is a preset boundary value, each respective angular section having a symmetry axis passing through a respective diagonal state of the signal constellation, which respective diagonal state has a modulus which is unique amongst the states in a same 2π

/M section of the plane; and

(b) secondly, boundary circles, centered at the origin of the signal constellation, of radius ##EQU4## the circles being equidistant from respective first and second consecutive circles, the respective first consecutive circle passing through a first respective plurality of states which each have a modulus value A1, the respective second consecutive circle passing through a second respective plurality of states which each have a modulus value A2, the respective first and second consecutive circles together forming a ring, the point of origin forming an innermost circle, a maximum amplitude of the received digitally modulated wave determining an outermost circle.

3. The circuit of claim 2 wherein:

(a) the digitally modulated wave is of the 64 QAM type;

(b) the preset boundary value satisfies the inequality θ

≦

18.92°

; and

(c) the selection zones comprise a respective ring segment for each of the 12 states defined by the following list of Cartesian coordinates (±

1,±

1), (±

3,±

3), (±

7,±

7 ).

4. The circuit of claim 1 wherein the first channel comprises a series arrangement of:

(i) a demodulator receiving said modulated wave and the output signal of the oscillator; and

(ii) a low-pass filter, coupled to an output of the demodulator, for producing a filtered signal X.

5. The circuit of claim 1 wherein the second channel comprises a series arrangement of:

(i) a phase shifter for shifting a phase of the output signal of the oscillator through 90°

;

(ii) a demodulator receiving the digitally modulated wave and an output signal of the phase shifter; and

(iii) a low-pass filter, coupled to an output of the demodulator, for producing a filtered signal Y.

6. The circuit of claim 1 wherein the converting means comprises:

(a) means for storing the comparator signal; and

(b) an amplifying filter, coupled to receive the comparator signal from the storing means, for producing the error signal ε

(φ

).

7. The circuit of claim 2 wherein

(a) the selection zones further comprise second ring segments for respective adjacent non-diagonal states of the signal constellation having a same modulus within a same 2π

/M section of the plane, said second ring segments being defined by the intersections of two respective regions;

(i) first, subsections of respective angular sections (θ

, -θ

), which respective angular sections correspond to a phase difference φ

between a signal point of the digitally modulated wave and a corresponding state of the signal constellation, such that |φ

|<

θ

, where θ

is said preset boundary value, each respective angular section having a symmetry axis passing through a respective non-diagonal state of the signal constellation, which subsections contain signal points which for which the signs of the following two phase differences are the same;

(A) the phase difference φ

with respect to a corresponding state; and

(B) a second phase difference φ

with respect to a state adjacent to the corresponding state are the same; and

(ii) secondly, boundary circles, centered at the origin of the signal constellation, of radius ##EQU5## the circles being equidistant from respective first and second consecutive circles, the respective first consecutive circle passing through a first respective plurality of states which each have a modulus value A1, the respective second consecutive circle passing through a second respective plurality of states which each have a modulus value A2, the respective first and second consecutive circles together forming a ring.

8. The circuit of claim 7 wherein

(a) the digitally modulated wave is of the 64 QAM type;

(b) the preset boundary value θ

satisfies the inequality 18.92°

<

θ

≦

22.62°

;

(c) the ring segments comprise a respective first ring segment for each of the 12 states defined by the following list of Cartesian coordinates (±

1,±

1), (±

3,±

3), and (±

7,±

7); and

(d) said second ring segments comprise a respective second ring segments for each of the 8 states defined by the following list of Cartesian coordinates (±

5,±

7), (±

7,±

5).

9. The circuit of claim 7 wherein

(a) the digitally modulated wave is of the 64 QAM type;

(b) the preset boundary value θ

satisfies the inequality 22.62°

<

θ

≦

28.07°

;

(c) the ring segments comprise a respective first ring segment for each of the 12 states defined by the following list of Certesian coordinates (±

1,±

1), (±

3,±

3), and (±

7,±

7); and

(d) said second ring segments comprise a respective second ring segment for each of the 8 states defined by the following list of Cartesian coordinates (±

5,±

1), (±

1,±

5)

10. The circuit of claim 1 wherein

(a) the first channel comprises a series arrangement of:

(i) a first demodulator receiving said modulated wave and the output signal of the oscillator; and

(ii) a low-pass filter, coupled to an output of the first demodulator, for producing a filtered signal X;

(b) the second channel comprises a series arrangement of;

(i) a phase shifter for shifting a phase of the output signal of the oscillator through 90°

;

(ii) a second demodulator receiving the digitally modulated wave and an output signal of the phase shifter; and

(iii) a low-pass filter, coupled to an output of the second demodulator, for producing a filtered signal Y; and

(c) the phase comparing means further comprises a memory, addressable by the signals X and Y to supply data relating to a received signal point that falls within one of the selection zones as well as an amplitude and sign of the error signal.

11. The circuit of claim 10 wherein

(a) the memory has an output for supplying p bits, one of the p bits relating to whether the received signal point is in one of the selection zones;

(b) the phase comparing means further comprises

(i) first and second analog-to-digital converters coupled in the first and second channels, respectively, for receiving Cartesian coordinates X and Y of the received signal point, the first and second converters producing data that addresses the memory;

(ii) a logic OR gate have a first input activated by the one bit and a second input for receiving an external locked/unlocked signal;

(iii) a logic AND gate having a first input coupled to receive an output signal of the OR gate, a second input coupled to receive the basic clock signal H, and an output, and AND gate being for

(A) suppressing the edges in the basic clock signal H when the unlocked signal is received and the received signal point is in one of the selection zones; and

(B) validating the edges in the basic clock signal H when the locked signal is received,

so that the sampling clock signal appears at an output of the AND Gate;

(iv) p-1 triggers, activated by the sampling clock signal, for receiving p-1 bits form the memory; and

(v) a digital-to-analog converter coupled to outputs of the p-1 triggers; and

(c) the apparatus further comprises an amplifying filter coupled between the digital-to-analog converter and the control input of the oscillator.

12. The circuit of claim 11 wherein p=2, a first bit being for validating the comparator signal and a second bit for providing a constant amplitude phase difference sign.

13. The circuit of claim 11 wherein p=3, a first bit being for validating the comparator signal and second and third bits being for providing an amplitude and a phase difference sign.

14. The apparatus of claim 10 wherein the memory is a PROM.

15. Apparatus for use in a circuit for recovering a carrier from a digitally modulated wave having a phase symmetry 2π

/M, where M is an integer representing a symmetry order of a modulation scheme of said digitally modulated signal, said modulation scheme corresponding to a signal constellation having states, which states are representable using a graphic representation in polar coordinates by a function F(A,Φ

), where A and Φ

represent modulus and phase, respectively, of the states in the signal constellation, the apparatus comprising;

(a) phase comparing means, coupled to outputs of a first, in-phase demodulation channel and of a second, quadrature-phase demodulation channel and coupled to receive a basic recovered clock signal H, for determining and validating a comparator signal, the phase comparing means alternatively operating as phase detector and as a frequency detector and comprising means for selecting received signal points using selection zones, said selection zones being defined with respect to said graphic representation as located around certain states of the signal constellation, said selection zones appearing in said graphic representation as ring segments, the comparator signal being for supplying to control a voltage-controlled oscillator which in turn controls demodulation in the first and second channels, and

(b) means for producing a variable rate sampling clock signal which reproduces the basic clock signal H by discarding certain edges, said producing means;

(i) when the circuit is in acquisition mode (unlocked), validating the basic clock signal H only for the selection zones; and

(ii) when the circuit is in permanent mode (locked), validating all edges of the clock signal H for forming the sampling clock signal;

said sampling clock signal being supplied to the comparing means to control validating of the comparator signal.

16. The apparatus of claim 15 wherein each ring segment comprises an intersection of two respective regions:

(i) first, a respective angular section (-θ

,θ

) corresponding to a phase difference φ

between a signal point of the received digitally modulated wave and a corresponding state of the signal constellation, such that the absolute value of φ

is less than θ

, where θ

is a preset boundary value, each respective angular section having a symmetry axis passing through a respective diagonal state of the signal constellation, which respective diagonal state has a modulus which is unique amongst the states in a same 2π

/M section of the plane; and

(ii) secondly, boundary circles, centered at the origin of the signal constellation, of radius ##EQU6## the circles being equidistant from respective first and second consecutive circles, the respective first consecutive circle passing through a first respective plurality of states which each have a modulus value A1, the respective second consecutive circle passing through a second respective plurality of states which each have a modulus value A2, the respective first and second consecutive circles together forming a ring, the point of origin forming an innermost circle, a maximum amplitude of the received digitally modulated wave determining an outermost circle.

17. The apparatus of claim 16 wherein:

(a) the digitally modulated wave is of the 64 QAM type;

(b) the preset boundary value satisfies the inequality θ

≦

18.92°

; and

(c) the selection zones comprise a respective ring segment for each of the 12 states defined by the following list of Cartesin coordinates (±

1,±

1), (±

3,±

3), (±

7,±

7).

18. The circuit of claim 15 wherein p1 (a) the selection zones further comprise second ring segments for respective adjacent non-diagonal states of the signal constellation having a same modulus within a same 2π

/M section of the plane, said second ring segments being defined by the intersections of two respective regions;

(i) first, subsections of respective angular sections (θ

,-θ

), which respective angular sections correspond to a phase difference φ

between a signal point of the digitally modulated wave and a corresponding state of the signal constellation, such that |φ

|<

θ

, where θ

is said preset boundary value, each respective angular section having a symmetry axis passing through a respective non-diagonal state of the signal constellation, which subsections contain signal points which for which the signs of the following two phase differences are the same;

(A) the phase difference φ

with respect to a corresponding state; and

(B) a second phase difference φ

with respect to a state adjacent to the corresponding state are the same; and

(ii) secondly, boundary circles, centered at the origin of the signal constellation, of radius ##EQU7## the circles being equidistant from respective first and second consecutive circles, the respective first consecutive circle passing through a first respective plurality of states which each have a modulus value A1, the respective second consecutive circle passing through a second respective plurality of states which each have a modulus value A2, the respective first and second consecutive circles together forming a ring.

19. The circuit of claim 18 wherein

(a) the digitally modulated wave is of the 64 QAM type;

(b) the preset boundary value θ

satisfies the inequality 18.92°

<

θ

≦

22.62°

;

(c) the ring segments comprise a respective first ring segment for each of the 12 states defined by the following list of Cartesian coordinates (±

1,±

1), (±

3,±

3), and (±

7,±

7); and

(d) said second ring segments comprise a respective second ring segment for each of the 8 states defined by the following list of Cartesian coordinates (±

5,±

7), (±

7,±

5).

20. The circuit of claim 18 wherein

(a) the digitally modulated wave is of the 64 QAM type;

(b) the preset boundary value θ

satisfies the inequality 22.62°

<

θ

≦

28.07°

;

(c) the ring segments comprise a respective first ring segment for each of the 12 states defined by the following list of Cartesian coordinates (±

1,±

1), (±

3,±

3), and (±

7,±

7); and

(d) said second ring segments comprise a respective second ring segment for each of the 8 states defined by the following list of Cartesian coordinates (±

5,±

1), (±

1,±

5).