Shadow memory system for storing variable backup blocks in consecutive time periods

• US 4,959,774 A
• Filed: 06/30/1989
• Issued: 09/25/1990
• Est. Priority Date: 07/06/1984
• Status: Expired due to Fees

• Current Assignee: Ampex Corporation (Delta Information Systems, Inc.)
• Original Assignee: Ampex Corporation (Delta Information Systems, Inc.)
• Inventors: Davis, John E.
• Primary Examiner(s): Lee, Thomas C.
• Application Number:
  US07/374,614
• Time in Patent Office: 452 Days
• Field of Search: 364/200, 364/900, 364/134, 365/226, 365/228, 365/229, 371/12, 371/32, 371/61, 371/66
• US Class Current: 714/6.1
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30

Abstract

A highly reliable shadow memory system is able to survive multiple fast sequence power failures and includes a volatile main memory and a shadow memory subsystem which continually monitors write accesses to the main memory. The shadow memory subsystem includes a disk drive or shadow memory storing a copy of the data in main memory. As the main memory contents are altered, the shadow memory is continually updated to reflect the changes while main utility power is available. In the event of a main utility power failure, backup power is required to store main memory data in the shadow memory for only a few storage locations for which the updating of the shadow memory may lag main memory data changes. Consequently, only a small portion of available battery backup power is required to preserve all main memory data and the system can withstand multiple rapid succession power failures without loss of data.

Claims

1. A data storage system for a host computer having a CPU bus, comprising:

a volatile main memory coupled to the CPU bus;

a usage monitor memory having a plurality of address locations;

bus monitor means for monitoring data transfers between the volatile memory and the CPU bus and, in response to each write type of data transfer between the volatile main memory and the CPU bus, storing in the usage monitor memory an indication of the data transfer;

a shadow memory subsystem including a nonvolatile data store, the shadow memory subsystem comprising means, coupled to said usage monitor memory, for determining when said bus monitor means is not accessing said usage monitor memory and for providing access of the shadow memory subsystem to said usage monitor memory upon which determination and means for sequentially searching variable numbers of the usage monitor memory address locations during consecutive variable length time periods when the bus monitor means is not accessing the usage monitor memory for an indication of a data transfer, and continually searching the entire plurality of address locations during said consecutive time periods, means, upon finding an indication, for responding to the indication by reading from the volatile main memory any data stored at a location to which the indication relates and writing the data read from the volatile main memory to the nonvolatile data store, and means for erasing the indication from the usage monitor memory.

2. The data storage system according to claim 1 above, further comprising a power supply subsystem coupled to provide operating power to the volatile main memory in response to utility supplied power, the usage monitor memory, the bus monitor means and the shadow memory subsystem, the power supply subsystem including an energy source storing sufficient energy to maintain the data storage system in a functioning condition for a limited time following a utility power failure.

3. The data storage system according to claim 1 above, wherein each address location within the usage monitor memory corresponds to a predetermined plurality of address locations in the main memory.

4. The data storage system according to claim 2 above, wherein each bit of data stored by the usage monitor memory corresponds to a predetermined plurality of address locations in the main memory.

5. The data storage system according to claim 4 above, wherein each address location in the main memory stores a multibit word.

6. The data storage system according to claim 2 above, wherein the power supply subsystem includes an AC power monitor coupled to sense the availability of power on utility power lines and to generate a power loss indication signal whenever the power level on the utility power lines is insufficient to support normal operation of the data storage system.

7. The data storage system according to claim 6 above, wherein the shadow memory subsystem is coupled to receive the power loss indication signal and further comprise means responsive to the power loss indication signal for inhibiting further data transfers between the main memory and the CPU bus, and wherein said means for continually searching responds to the power loss indication signal by searching the usage monitor memory and said reading and writing means and erasing means responding to each indication of a data transfer by storing all data in the main memory corresponding to the indication in the nonvolatile data store and erasing the indication respectively, and said shadow memory subsystem further comprises means, when the usage monitor memory has been cleared of all indications of data transfers, for generating a power down command commanding the power supply subsystem to terminate the supply of power to the data storage system and thereby conserve energy stored by the energy source.

8. The data storage system according to claim 1 above, wherein the nonvolatile data store is a magnetic remanent flux type of store.

9. The data storage system according to claim 1 above, wherein the nonvolatile data store is a disk drive.

10. The data storage system according to claim 1 above, wherein the nonvolatile data store is a disk drive of type having a sealed container enclosing a rigid magnetic disk and at least one movable read/write head.

11. The data storage system according to claim 1 above, further comprising a memory controller coupled between the main memory and the host CPU bus and simulating a disk drive controller to enable data transfers between the host CPU bus and main memory as though the main memory were a disk drive.

12. A data storage system for a host CPU having a CPU bus, comprising:

a volatile main memory having a plurality of blocks of addressable storage locations;

a main memory bus;

memory controller means, coupled to the main memory bus, for communicating data between the main memory and the CPU bus;

a usage monitor memory having a plurality of storage locations each corresponding to a predetermined block of addressable storage locations in the main memory;

memory multiplexer means, coupled to the usage monitor memory, for selectively accessing the usage monitor memory;

bus monitor circuit means, coupled to the main memory bus and the memory multiplexer means, for monitoring data transfers between the main memory and the memory controller for communication over the host CPU bus and for responding to each write type of data transfer by assuring that an indication of memory usage is stored in the usage monitor memory at a storage location which corresponds to the main memory block at which the write data transfer occurs;

a power supply subsystem coupled to receive power from an externally supplied interruptible power source and including a limited duration uninterruptible power source, the power supply subsystem including means for supplying power to the data storage system with the supplied power being taken from the interruptible power source when possible and otherwise from the interruptible power source, the power supply subsystem including a power monitor coupled to monitor the interruptible power source and generate a power supply signal indicating whether or not the power available from the interruptible power source is adequate to operate the data storage system; and

a shadow memory subsystem including a nonvolatile data store, the shadow memory subsystem being coupled to the memory multiplexer means and to the power supply subsystem, the shadow memory subsystem further including;

means for continually searching while the power supply signal indicates an availability of adequate power for indications of main memory usage stored in the usage monitor memory by making repetitive usage monitor memory read accesses when the bus monitor means is not accessing the usage monitor memory and, upon finding an indication of memory usage, executing a shadow storage operation upon main memory data corresponding to the indication by reading data from all address locations of the main memory within the block which corresponds to the indication, writing the data into corresponding locations in the nonvolatile data store and erasing the indication of memory usage, and

means for operating, while the power supply signal indicates a nonavailablity of adequate power, to generate a main memory inhibit signal inhibiting further data transfers between the main memory and the CPU bus, to search each location of the usage monitor memory for an indication of main memory usage, to execute a shadow storage operation for each indication of main memory usage, and to command termination of the supply of power to the data storage system.

13. The data storage system according to claim 12 above, wherein the power supply subsystem includes a power control circuit coupled to terminate distribution of power to the data storage system in response to a command generated by the shadow memory subsystem to terminate power, and to reinitiate distribution of power to the data storage system following termination of power whenever the interruptable power source supplies sufficient power to operate the data storage system.

14. The data storage system according to claim 13 above, wherein the shadow memory subsystem further operates upon reinitiation of the distribution of power following a termination of power distribution to restore the data content of the main memory by reading the data from the nonvolatile memory and writing it into the main memory and then terminate the inhibiting of data transfers between the main memory and the CPU bus.

16. The data storage system according to claim 12 above, further comprising a memory read/write circuit coupled between the shadow memory subsystem and the main memory, the memory read/write circuit being responsive to read and write commands from the shadow memory subsystem to provide address and control signals to the main memory which are required for data transfers therewith.

15. A data storage system for a host CPU having a CPU bus, comprising:

a volatile main memory having a plurality of blocks of addressable storage locations;

a main memory bus;

memory controller means, coupled to the main memory bus, for communicating data between the main memory and the CPU bus;

a usage monitor memory having a plurality of storage locations each corresponding to a predetermined block of addressable storage locations in the main memory;

memory multiplexer means, coupled to the usage monitor memory, for selectively accessing the usage monitor memory,

bus monitor circuit means, coupled to the main memory bus and the memory multiplexer means, for monitoring data transfers between the main memory and the memory controller for communication over the host CPU bus and for responding to each write type of data transfer by assuring that an indication of memory usage is stored in the usage monitor memory at a storage location which corresponds to the main memory block at which the write data transfer occurs;

a power supply subsystem coupled to receive power from an externally supplied interruptible power source and including a limited duration uninterruptible power source, the power supply subsystem including means for supplying power to the data storage system with the supplied power being taken from the interruptible power source when possible and otherwise from the uninterruptible power source, the power supply subsystem including a power monitor coupled to monitor the interruptible power source and generate a power supply signal indicating whether or not the power available from the interruptible power source is adequate to operate the data storage system;

a shadow memory subsystem including a nonvolatile data store, the shadow memory subsystem being coupled to the memory multiplexer means and to the power supply subsystem, the shadow memory subsystem further including;

means for searching while the power supply signal indicates an availability of adequate power for indications of main memory usage stored in the usage monitor memory by making repetitive usage monitor memory read accesses and, upon finding an indication of memory usage, executing a shadow storage operation upon main memory data corresponding to the indication by reading data from all address location of the main memory within the block which corresponds to the indication, writing the data into corresponding locations in the nonvolatile data store and erasing the indication of memory usage, and

means for operating, while the power supply signal indicates a nonavailability of adequate power, to generate a main memory inhibit signal inhibiting further data transfer between the main memory and the CPU bus, to search each location of the usage monitor memory for an indication of main memory usage, to execute a shadow storage operation for each indication of main memory usage, and to command termination of the supply of power to the data storage system; and

a bus request circuit coupling the shadow memory subsystem to the memory controller means, the bus request circuit operates while adequate power is available to respond to main memory access requests from the shadow memory subsystem by communicating to the memory controller a relatively low priority request for access to the main memory, and being responsive to the inhibit signal to make a highest priority request to the memory controller for access to the main memory.

17. A backup data storage system for a primary data store having a plurality of storage locations addressable by a data processing system, each primary data store addressable storage location being assigned to one of a plurality of primary store data blocks, each containing the data stored by all of the addressable storage locations assigned thereto, the backup data storage system comprising:

first means for storing a write indication at each of a plurality of addressable storage locations, each of which has a predetermined correspondence with one of the data block;

means for writing a write indication into the first means for storing a write indication each time data is written by the data processing system into the primary data store, the write indication being stored at a location corresponding to a primary store data block into which the data has been written;

second means for storing a plurality of backup data blocks, each corresponding to a different primary store data block; and

data processing means, connected to the first storing means, the means for writing a write indication, the second storing means, and the primary data store, comprising means coupled to the firs storing means for determining when said writing means is not accessing the first storing means, means for continually accessing said first storing means when said first storing means is available for data communication and for repetitively reading sequential addressable storage locations of the first storing means, wherein the number of addressable storage locations read varies with the time during which said first storing means is available for data communications, and means, upon reading a write indication from a currently addressed storage location, for copying the primary store data block corresponding thereto to the corresponding backup data block stored by the second storing means.

18. The backup data storage system according to claim 17 above,

wherein the data processing means further includes means responsive to a failure of a main power supply for the backup data storage system for preserving primary data store data by

(1) generating a signal that is connected to means for disabling data communication between the primary data store and the data processing system,

(2) sequentially reading each addressable storage location of the first means for storing a write indication and each time a write indication is read from a currently addressed location, copying the primary store data block corresponding thereto to the corresponding backup data block stored by the second means for storing a plurality of backup data blocks, and

(3) generating a power termination signal commanding that power distribution to the primary data store be terminated.

19. The backup data storage system according to claim 18 above, wherein the data processing means further includes means responsive to a restoration of power from the main power supply for restoring primary data store data by

(1) generating said signal that is connected to means for disabling data communication between the primary data store and the data processing system,

(2) copying each backup data block to the primary store data block corresponding thereto stored by the primary data store, and

(3) terminating the generating of said signal that is connected to means for disabling data communication.

20. The backup data storage system according to claim 19 above, further comprising means for supplying power coupled to receive power from the main power supply when available and including an alternative source of power that is used when power is not available from the main power supply, the power supplying means including power switching means responsive to the power termination signal that is connected to supply power to the primary data store with the power to the primary data store being switched off in response to receipt of the power termination signal and switched on in the absence of the power termination signal.

21. A method of backing up data in a primary data store having a plurality of addressable storage locations storing the data and coupled for communication with a data processing system, the method using a usage monitor memory having a plurality of addressable storage locations and a nonvolatile shadow data store, the method comprising the steps of:

assigning each addressable storage location in the primary data store to one of a plurality of different blocks of storage locations;

establishing a correspondence between each of the blocks of locations and a different addressable storage location in the usage monitor memory;

writing a data write indication into the usage monitor memory each time data is written into an addressable storage location of the primary data store from the data processing system, the data write indication being written to a usage monitor memory location corresponding to the block of storage locations to which is assigned the primary data store addressable location at which the data was written; and

continually accessing the usage monitor memory when the usage monitor memory is not being written with write data indications and repetitively reading in sequence the addressable storage locations of the usage monitor memory which correspond to a block of locations in the primary data store, and upon reading a data write indication from any given location in the usage monitor memory

(1) copying to the nonvolatile shadow data store all data stored by the primary data store at addressable locations assigned to the block of locations corresponding to the given location in the usage monitor memory, and

(2) clearing the data write indication from the given location in the usage monitor memory.

22. The method according to claim 21 above, further comprising the steps of:

executing a data preservation sequence upon the occurrence of a loss of power from a primary power source, the data preservation sequence comprising the steps of;

(1) disabling data communication between the primary data store and the data processing system,

(2) sequentially reading each addressable storage location of the usage monitor memory and, upon reading a data write indication from any given location in the usage monitor memory, copying to the shadow data store all data stored by the primary data store at addressable locations assigned to the block of locations corresponding to the given location in the usage monitor memory, and

(3) commanding a power preservation mode in which reduced power is used by the primary data store pending restoration of power from the primary power source.

23. The method according to claim 22 above, further comprising the steps of:

executing a data restoration sequence upon the restoration of power from the primary power source following a loss of power from the primary power source, the data restoration sequence comprising the steps of;

(1) disabling data communication between the primary data store and the data processing system,

(2) copying an image of primary data store data stored by the shadow data store to the primary data store,

(3) enabling communication of data between the primary data store and the data processing system, and

(4) executing said continually reading step.