Electrically erasable programmable read-only memory with NAND cell structure

• US 4,959,812 A
• Filed: 12/27/1988
• Issued: 09/25/1990
• Est. Priority Date: 12/28/1987
• Status: Expired

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Masuoka, Fujio, Kirisawa, Ryouhei, Shirota, Riichiro, Momodomi, Masaki, Itoh, Yasuo, Ohuchi, Kazunori
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/289,702
• Time in Patent Office: 637 Days
• Field of Search: 365/182, 365/104, 365/185, 365/230.03, 365/218, 357/23.5, 357/45
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

Claims

1. A non-volatile dynamic semiconductor memory device comprising:

(a) a semiconductive substrate having a major surface;

(b) a semiconductive well region formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device;

(c) parallel bit lines provided above said substrate;

(d) rewritable memory cells connected to said bit lines, said memory cells comprising NAND cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer, a control gate and semiconductive layers formed in said well region to function as sources and drains, and said well region functioning as a surface breakdown prevention layer; and

(e) control means for writing data into memory cells of a selected NAND cell block sequentially during a data write mode subsequent to the data erase mode, said control means applying, when a certain memory cell of said selected NAND cell block is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well region.

2. The device according to claim 1, wherein said substrate has a first conductivity type, said well region has a second conductivity type and said semiconductive layers have the first conductivity type.

3. The device according to claim 1, wherein said substrate and said well region have a first conductivity type and said semiconductive layers have a second conductivity type;

and wherein said device further comprises an additional well region of the second conductivity type formed in said substrate so as to surround said well region.

4. The device according to claim 3, wherein said well regions are connected to a common well potential.

5. The device according to claim 1, wherein said selected NAND cell block comprises:

a first selection transistor provided at one end of said selected NAND cell block and selectively rendered conductive for electrically connecting said selected NAND cell block to a corresponding bit line associated therewith; and

a second selection transistor provided at the other end of said selected NAND cell block and selectively rendered conductive for electrically connecting said selected NAND cell block to said well area, said second selection transistor being rendered nonconductive during the data write mode so as to prevent leakage of current between said corresponding bit line and said substrate.

6. The device according to claim 1, wherein each of said NAND cell blocks comprises:

an erase gate layer provided insulatingly over said substrate so as to extend substantially parallel to said series array of memory cell transistors and sandwiched insulatingly by said charge accumulation layer and said control gate of each of said memory cell transistors, said erase gate layer overlapping said charge accumulation layer and said charge accumulation layer and said control gate being capacitively coupled to each other by said erase gate layer.

14. The device according to claim 1, wherein said control means erases data stored in all said memory cells simultaneously during a data erase mode of said memory device.

7. An erasable programmable read-only memory device comprising:

(a) a semiconductive substrate having a semiconductive well layer formed in its major surface;

(b) parallel bit lines provided over said substrate;

(c) parallel word lines intersecting said bit lines insulatingly;

(d) double-gate field effect transistors provided at intersections of said bit lines and said word lines for functioning as memory cells, said transistors including a cell array which has a series-circuit of cell transistors constituting a NAND cell block, each of said cell transistors having semiconductor layers serving as a source and a drain thereof, an electrically floating gate layer serving as a charge accumulation layer and a control gate layer connected to a corresponding word line, said semiconductor layers being formed in said well layer;

(e) a field effect transistor provided at one end of said NAND cell block and selectively rendered conductive for serving as a first selection transistor;

(f) a field effect transistor provided at the other end of said NAND cell block and selectively rendered conductive for serving as a second selection transistor; and

(g) driving means for, when said NAND cell block is selected during a data write mode of said device, (1) rendering said first selection transistor conductive to electrically connect said NAND cell block to a corresponding bit line associated therewith to which write data is applied, (2) rendering said second selection transistor nonconductive to electrically disconnect said NAND cell block from said well layer, and (3) writing data into memory cells of said NAND cell block sequentially, said driving means changing a potential of said well layer to have a level different from that of a potential of said well layer in a simultaneous erase mode prior to the data write mode of said device.

8. The device according to claim 7, wherein said driving means writes data into memory cells of said NAND cell block in a predetermined sequence in which a cell transistor adjacent to said second selection transistor is subjected to writing first and a cell transistor adjacent to said first selection transistor is subjected to writing last.

9. The device according to claim 8, wherein said driving means applies, when a certain memory cell of said NAND cell block is subjected to writing, to said control gate of said certain memory cell a first voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well layer and to the remaining memory cells of said NAND cell block a second voltage lower than the first voltage.

10. The device according to claim 9, wherein said substrate has a first conductivity type, said well layer has a second conductivity type and said semiconductive layers have the first conductivity type.

11. The device according to claim 10, wherein said driving means applies to said well layer one of a "H" level potential and a "L" level potential during the simultaneous erase mode and the other of the "H" level potential and the "L" level potential during the data write mode.

12. The device according to claim 9, wherein said substrate and said well layer have a first conductivity type and said semiconductive layers have a second conductivity type;

and wherein said device further comprises an additional well layer of the second conductivity type formed in said substrate so as to surround said well layer.

13. The device according to claim 12, wherein said driving means applies to said well layers a "L" level potential during the simultaneous erase mode and a "H" level potential during the data write mode.

15. A non-volatile dynamic semiconductor memory device comprising:

a semiconductor substrate having a major surface;

a semiconductor well region formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device;

parallel bit lines provided above said substrate;

rewritable memory cells connected to said bit lines, said memory cells comprising NAND cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer, a control gate and semiconductor layers formed in said well region to function as sources and drains, and said well region functioning as a surface breakdown prevention layer;

control means for erasing data stored in all said memory cells simultaneously during a data erase mode of said memory device and writing data into memory cells of a selected NAND cell block sequentially during a data write mode subsequent to the data erase mode, said control means applying, when a certain memory cell of said selected NAND cell block is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well region;

a first selection transistor provided at one end of said selected NAND cell block and selectively rendered conductive for electrically connecting said selected NAND cell block to a corresponding bit line associated therewith; and

a second selection transistor provided at the other end of said selected NAND cell block and selectively rendered conductive for electrically connecting said selected NAND cell block to said well area, said second selection transistor being rendered nonconductive during the data write mode so as to prevent leakage of current between said corresponding bit line and said substrate.