Ode through holes and butt edges without edge dicing

• US 4,961,821 A
• Filed: 11/22/1989
• Issued: 10/09/1990
• Est. Priority Date: 11/22/1989
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Drake, Donald J., Campanelli, Michael R., Hawkins, William G., Tellier, Thomas A.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US07/440,296
• Time in Patent Office: 321 Days
• Field of Search: 156/643, 156/644, 156/647, 156/633, 156/648, 156/651, 156/653, 156/657, 156/659.1, 156/661.1, 156/662, 346/1.1, 346/140 R, 437/226, 437/228, 437/241
• US Class Current: 438/21
• CPC Class Codes: B41J 2/1603 of the front shooter type
• CPC Class Codes: B41J 2/1628 dry etching
• CPC Class Codes: B41J 2/1629 wet etching
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

At least one through opening of predetermined location and dimensions is fabricated in a (100) silicon wafer by orientation dependent etching method after completion of integrated circuits on the wafer, the opening extending through the wafer between a circuit surface of the wafer and an opposite parallel base surface of the wafer and having a predetermined location relative to the integrated circuit on the circuit surface of the wafer. The method includes the steps of fabricating the integrated circuit on the circuit surface of the wafer; applying an etch resistant layer of plasma solicon nitride on the circuit and base surfaces of the wafer; patterning the etch resistant plasma silicon nitride layer on the circuit surface to define an upper etch opening having a location and dimensions which define the predetermined location and dimensions of the through opening; and patterning the plasma silicon nitride layer on the base surface to produce a lower etch opening aligned with the upper etch opening within a predetermined tolerance. The wafer is then anisotropically etched to produce a first recess corresponding to the upper etch opening in the circuit surface and a second recess corresponding to the lower etch opening in the base surface, each of the first and second recesses being bounded by (111) plane side walls. The anisotropic etching of the second recess intersects the first recess to form the through opening bounded by (111) plane side walls and has its predetermined dimensions and location defined by the patterning of the upper etch opening.

Claims

1. A method of fabricating at least one through opening of predetermined dimensions in a (100) silicon wafer by orientation dependent etching after completion of integrated circuits on the wafer, the opening extending through the wafer between a circuit surface of the wafer and an opposite parallel base surface of the wafer and having a predetermined location relative to the integrated circuit on the circuit surface of the wafer, the method comprising the steps of:

fabricating the integrated circuit on the circuit surface of the wafer;

applying an etch resistant layer of plasma silicon nitride on the circuit and base surfaces of the wafer;

patterning the etch resistant plasma silicon nitride layer on the circuit surface to define an upper etch opening having a location and dimensions which define the predetermined location and dimensions of the through opening;

patterning the plasma silicon nitride layer on the base surface to produce a lower etch opening aligned with the upper etch opening within a predetermined tolerance; and

anisotropic etching the wafer to produce a first recess corresponding to the upper etch opening in the circuit surface and a second recess corresponding to the lower etch opening in the base surface, each of the first and second recesses being bounded by (111) plane side walls, the anisotropic etching of the second recess intersecting the first recess to form the through opening bounded by (111) plane side walls and having its predetermined dimensions and location defined by the patterning of the upper etch opening.

2. The method of claim 1 wherein the layer of etch resistant plasma silicon nitride is applied at a temperature in the range of 250°

C. to 450°

C.

3. The method of claim 2 wherein the layer of etch resistant plasma silicon nitride is applied at a temperature of about 350°

C.

4. The method of claim 1 wherein the anisotropic etching of the first and second recesses forms the through hole with the predetermined dimension regardless of thickness of the wafer between the circuit and base surfaces.

5. The method of claim 1 wherein the step of applying the etch resistant layer of plasma silicon nitride on the circuit and base surfaces of the wafer includes the steps of applying the etch resistant plasma silicon nitride layer on one of the circuit and base surfaces to form a first coated surface, placing the first coated surface on a graphite boat, and applying the etch resistant plasma silicon nitride layer on the other of the circuit and base surfaces to form a second coated surface.

6. The method of claim 5 wherein the first coated surface is the circuit surface.

7. The method of claim 1 wherein the steps of patterning the plasma silicon nitride layer on the circuit and base surfaces are performed by using double side aligning etch patterns on the circuit and base surfaces.

8. The method of claim 1 wherein the lower etch opening is larger than the upper etch opening.

9. The method of claim 1 wherein the anisotropic etching of the first and second recesses forms the through hole with the predetermined dimensions and location regardless of misalignment within the predetermined tolerance of the upper and lower etch openings provided the first and second recesses intersect during anistropic etching.

10. The method of claim 1 wherein the step of patterning the etch resistant plasma silicon nitride layer on the circuit surface comprises the steps of:

additionally patterning the etch resistant plasma silicon nitride layer on the circuit surface to produce a contact pad opening at a predetermined location on the circuit surface;

applying a low temperature oxide layer over the circuit surface to expose the upper etch opening and cover the contact pad opening;

applying an additional plasma silicon nitride layer over the low temperature oxide layer, the additional plasma silicon nitride layer being patterned to expose the upper etch opening and cover the contact pad opening; and

further comprising,

after the step of anisotropic etching, removing the additional plasma silicon nitride layer to expose the low temperature oxide layer and subsequently removing the low temperature oxide layer to expose the plasma silicon nitride layer having the contact pad opening.

11. The method of claim 1 wherein the through opening bounded by (111) plane side walls subsequently serves to define a butting surface for the wafer.

12. The method of claim 1 wherein the through openings bounded by (111) plane side walls subsequently serves as an ink conduit in a wafer used to form a printhead for an ink jet printing device.

13. The method of claim 1 wherein a plurality of through openings are formed in the wafer and the silicon wafer is separated into subunits along each through opening, the (111) plane side walls of the through openings defining butting surfaces on opposite sides of each subunit.

14. The method of claim 1 wherein the anisotropic etching of the first and second recesses is controlled to stop the etching at first and second predetermined depths, respectively, the through opening formed by the intersection of the first and second recesses including a buttable edge defined by the intersection of the (111) plane side walls of the first and second recesses and located at a distance corresponding to the first predetermined depth from the circuit surface.

15. The method of claim 1 wherein the anisotropic etching of the first and second recess continues through the wafer to form the through opening with an etch ledge adjacent to the base surface.

16. A method for producing a buttable edge in a (100) silicon wafer by orientation dependent etching after processing of integrated circuits on the wafer, the edge being located between a circuit surface of the wafer and an opposite parallel base surface of the wafer, the method comprising the steps of:

fabricating the integrated circuits on the circuit surface of the wafer;

applying an etch resistant layer of plasma silicon nitride on the circuit and base surfaces of the wafer;

patterning the plasma silicon nitride layer on the base surface to produce a lower etch opening;

anisotropic etching the wafer to produce a recess corresponding to the lower etch opening in the base surface and bounded by (111) plane side walls, the recess having a first predetermined depth less than the thickness of the wafer;

reapplying an etch resistant plasma silicon nitride layer on the base surface to prevent further etching of the recess;

patterning the etch resistant plasma silicon nitride layer on the circuit surface to produce an upper etch opening having a predetermined location in alignment with the recess and predetermined dimensions with respect to the integrated circuits; and

anisotropic etching the wafer to produce a trough corresponding to the upper etch opening in the circuit surface and bounded by (111) plane side walls, the anisotropic etching of the trough continuing to a second predetermined depth to intersect the recess and form the buttable edge defined by the intersection of the (111) plane side walls of the recess and trough.

17. The method of claim 16 wherein the anisotropic etching of the wafer to form the trough of predetermined depth in the circuit surface defines the location of the buttable edge by controlling the intersection of the (111) plane side walls of the recess and trough.

18. The method of claim 16 further comprising the step of butting the buttable edge of one wafer against a buttable edge of an adjacent wafer.

19. A method for producing a buttable surface in a silicon (100) wafer by orientation dependent etching after processing of integrated circuits on the wafer, the buttable surface being located between a circuit surface of the wafer and an opposite parallel base surface, the method comprising the steps of:

forming by orientation dependent etching an alignment hole at a periphery of the wafer to define a (111) plane surface;

fabricating the integrated circuits on the circuit surface in alignment with the (111) surface;

applying an etch resistant layer of plasma silicon nitride on the circuit and base surfaces of the wafer;

patterning the etch resistant silicon nitride layer on the circuit surface to produce an upper etch opening;

anisotropic etching the wafer to produce a trough corresponding to the upper etch opening and bounded by (111) plane side walls, the trough having a first predetermined depth and defining a first buttable (111) surface;

reapplying an etch resistant plasma silicon nitride layer on the circuit surface to prevent further etching of the trough;

patterning the etch resistant silicon nitride layer on the base surface to produce two spaced lower etch openings, each opening being located on the base surface at a predetermined location with respect to the alignment hole, a first one of the openings being aligned with the trough; and

anisotropically etching the wafer to produce two recesses each corresponding to one of the lower etch openings and bounded by (111) plane side walls, a first one of the recesses corresponding to the first one of the lower etch openings having a second predetermined depth sufficient to intersect the trough, the anisotropic etching of the other of the recesses continuing through the wafer to define a second buttable surface parallel to a (111) plane surface of the alignment hole.

20. The method of claim 19 further comprising the step of butting the first buttable surface of one wafer against the second buttable surface of an adjacent wafer.

21. A method for producing a buttable edge in a (100) silicon wafer by orientation dependent etching, the edge being located between an upper surface of the wafer and an opposite base surface of the wafer, the method comprising the steps of:

applying an etch resistant layer on the upper and base surfaces of the wafer;

patterning the etch resistant layer on the base surface to produce a lower etch opening;

anisotropic etching the wafer to produce a recess corresponding to the lower etch opening in the base surface and bounded by (111) plane sidewalls, the recess having a first predetermined depth less than the thickness of the wafer;

reapplying an etch resistant layer on the base surface to prevent further etching of the recess;

patterning the etch resistant layer on the upper surface to produce an upper etch opening having a predetermined location in alignment with the recess and predetermined dimensions with respect to the upper surface; and

anisotropic etching the wafer to produce a trough corresponding to the upper etch opening in the upper surface and bounded by (111) sidewalls, the anisotropic etching of the trough continuing to a second predetermined depth to intersect the recess and form the buttable edge defined by the intersection of the (111) plane sidewalls of the recess and trough.

22. The method of claim 21 wherein the etch resistant layer is applied at a temperature in the range of 250°

C. to 450°

C.

23. The method of claim 22 wherein the etch resistant layers are applied at a temperature of about 350°

C.

24. The method of claim 21 wherein the etch resistant layer is plasma silicon nitride.

25. A method of producing a buttable surface in a (100) silicon wafer by orientation dependent etching, the buttable surface being located between an upper surface of the wafer and an opposite base surface of the wafer, the method comprising the steps of:

applying an etch resistant layer on the upper and base surfaces of the wafer;

patterning the etch resistant layer on the upper surface to produce an upper etch opening having a location and dimensions which define the predetermined location and dimensions of the buttable surface;

patterning the etch resistant layer on the base surface to produce a lower etch opening aligned with the upper etch opening within a predetermined tolerance; and

anisotropic etching the wafer to produce a first recess corresponding to the upper etch opening in the upper surface and a second recess corresponding to the lower etch opening in the base surface, each of the first and second recesses being bounded by (111) plane sidewalls, the anisotropic etching of the second recess intersecting the first recess to form the buttable surface bounded by (111) plane sidewalls and having its predetermined dimensions in a location defined by the patterning of the upper etch opening.

26. The method of claim 25 wherein the etch resistant layers are applied at a temperature between 250°

C. and 450°

C.

27. The method of claim 26 wherein the etch resistant layers are applied at about 350°

C.

28. The method of claim 25 wherein the etch resistant layer is plasma silicon nitride.

29. A method of fabricating a pagewidth printhead for an ink jet printing device, by butting together (100) silicon wafer subunits having butting edges, the method comprising the steps of:

obtaining a (100) silicon wafer having an upper surface and an opposite base surface;

applying an etch resistant layer on the upper and base surfaces of the wafer;

patterning the etch resistant layer on the upper surface to produce a plurality of upper etch openings having locations and dimensions which define predetermined locations and dimensions of a plurality of butting surfaces;

patterning the etch resistant layer on the base surface to produce a plurality of lower etch openings each aligned with a corresponding upper etch opening within a predetermined tolerance;

anisotropic etching the wafer to produce a plurality of upper recesses corresponding to the upper etch openings in the upper surface and a plurality of lower recesses corresponding to the lower etch openings in the base surface, each of the upper and lower recesses being bounded by (111) plane sidewalls, the anisotropic etching of the lower recesses intersecting the upper recesses and forming a plurality of through holes;

separating the wafer along the through holes to form at least one wafer subunit, the (111) plane sidewalls of the through holes defining butting surfaces on opposite sides of the at least one subunit, the butting surfaces having their predetermined dimensions and location defined by the patterning of the upper etch opening; and

aligning a series of subunits with their butting surfaces adjacent to and butting against one another to form an array with a length corresponding to a pagewidth.

30. The method of claim 29 wherein the etch resistant layers are applied at a temperature between 250°

C. and 450°

C.

31. The method of claim 30 wherein the etch resistant layers are applied at a temperature of about 350°

C.

32. The method of claim 29 wherein the etch resistant layer is plasma silicon nitride.

33. The method of claim 29 wherein integrated circuitry is fabricated on the upper surface of the wafer prior to application of the etch resistant layers.