Equalizing circuit for a sense amplifier

• US 4,962,324 A
• Filed: 01/03/1989
• Issued: 10/09/1990
• Est. Priority Date: 04/30/1988
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Hee-Choul
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Cunningham, T.
• Application Number:
  US07/292,769
• Time in Patent Office: 644 Days
• Field of Search: 307/350, 307/481, 307/451, 307/452, 307/530, 365/203, 365/205, 365/207, 365/208
• US Class Current: 327/51
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

This present invention provides an equalizing cicruit for a sense amplifier comprising a sense amplifier enable signal generation section which receives a sense amplifier equalizing signal and produces a sense amplifier enable signal. An equalizing control section is connected to receive a signal from the sense amplifier enable signal generation section and the sense amplifier equalizing signal. A first and second sense amplifier equalizing signal generation sections are connected to receive an output from the equalizing control section. A third sense amplifier equalizing signal generation section is connected to receive a signal through the second sense amplifier equalizing signal generation section.

Claims

1. An equalizing circuit for a sense amplifier comprising:

a sense amplifier enable signal generation means for receiving a sense amplifier equalizing signal and for generating a sense amplifier enable signal;

an equalizing control means for receiving both said sence amplifier equalizing signal and said sense amplifier enable signal for generating an equalizing control output signal therefrom;

a first equalizing signal generation means for receiving said equalizing control output signal for generating a first sense amplifier equalizing signal;

a second equalizing signal generation means for receiving said equalizing control output signal for generating a second sense amplifier equalizing signal; and

a third equalizing signal generation means for receiving said second sense amplifier equalizing signal for generating a third amplifier equalizing signal.

2. An equalizing circuit for a sense amplifier according to claim 1 wherein said equalizing control means generates a signal which has a low level portion for equalizing said sense amplifier.