Multi-user serial bus system

• US 4,962,378 A
• Filed: 11/09/1987
• Issued: 10/09/1990
• Est. Priority Date: 11/09/1987
• Status: Expired due to Fees

• Current Assignee: CIT Group Incorporated
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Fadem, Richard J.
• Primary Examiner(s): Weldon, Ulysses
• Application Number:
  US07/118,814
• Time in Patent Office: 1,065 Days
• Field of Search: 340/825.51, 340/825.5, 340/825.02, 340/825, 340/825.14, 370/85, 370/32, 370/24, 370/85.1, 370/85.6, 375/7, 375/36, 375/8, 375/9, 379/93, 379/96, 379/98, 379/194, 379/442, 379/161
• US Class Current: 370/447
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling

Abstract

A new, multi-user data communication system is presented which is inexpensive and does not require any hardware changes to the central processor/system host. The standard serial data input/output port of each terminal is adapted from the standard single-user configuration to a party line, multi-user configuration by the addition of a simple and inexpensive interface circuit within each terminal. After the interface circuits are installed, the terminals can be interconnected to each other and to the central processor/system host using standard serial cabling. The party line interface circuit allows each terminal to access the non-busy serial data bus on a first-come-first-served basis. An interference detector and interference handling circuit are provided also to prevent data errors in the event of a possible data collision.

Claims

1. A digital data communication system for transferring data between a plurality of terminals to a central processor, comprising:

a first serial data conductor connected between the central processor and the plurality of terminals for outputting data to the central processor;

a second serial data conductor connected between the central processor and the plurality of terminals for receiving data from the central processor;

a clear-to-send control conductor connected from the central processor to the plurality of terminals for enabling a data transfer between the central processor and one of the plurality of terminals;

request-to-send means for outputting a request-to-send indicator to the central processor enabling the data transfer from the central processor to one of the plurality of terminals;

means for detecting a not-busy condition of the first and second serial data conductors;

means responsive to the not-busy detecting means for controlling the outputting of data to the central processor from one of the plurality of terminals via the first serial data conductor on a first-come, first-served basis; and

delay means for preventing each terminal from initiating a data transfer for a preselected delay period after the cessation of the busy condition to provide the terminal and the central processor a period to respond to the data transfer therebetween.

2. The digital data communication system according to claim 1, further comprising interference detecting means connected to the first serial data conductor for detecting an interference condition of at least two terminals outputting data onto the first serial data conductor concurrently.

3. The digital data communication system according to claim 2, further comprising:

means responsive to the interference detecting means for interrupting the transfer of data from one of the terminals concurrently outputting data onto the first serial data conductor; and

means responsive to the interrupting means for clearing from the terminal interrupted during an interfering transfer of data the portion of the interrupted data remaining within the terminal.

4. A digital data communication system according to claim 1, wherein the first and second serial data conductors and the clear-to-send control conductor are parts of a standard RS 232 cable.

5. A digital data communication system according to claim 4, wherein the central processor has a RS 232 standard serial data port connected to all of the plurality of terminals via the standard RS 232 cable.

6. A digital data communication system for transferring data between a plurality of terminals to a central processor, comprising:

a first serial data conductor connected between the central processor and the plurality of terminals for outputting data to the central processor;

a second serial data conductor connected between the central processor and the plurality of terminals for receiving data from the central processor;

a clear-to-send control conductor connected from the central processor to the plurality of terminals for enabling a data transfer between the central processor and one of the plurality of terminals;

request-to-send means for outputting a request-to-send indicator to the central processor enabling the data transfer from the central processor to one of the plurality of terminals;

means for detecting a not-busy condition of the first and second serial data conductors;

means responsive to the not-busy detecting means for controlling the outputting of data to the central processor from one of the plurality of terminals via the first serial data conductor on a first-come, first-served basis;

a plurality of means for detecting a busy condition of the first and second serial data conductors, each located in a respective terminal, for controlling the outputting of data to the central processor by preventing each terminal not involved in a data transfer from initiating a data transfer as long as one of the first and second serial data conductors is in a busy condition;

interference detecting means connected to the first serial data conductor for detecting an interference condition of at least two terminals outputting data onto the first serial data conductor concurrently;

means responsive to the interference detecting means for interrupting the transfer of data from one of the terminals concurrently outputting data onto the first serial data conductor; and

means responsive to the interrupting means for clearing from the terminal interrupted during an interferring transfer of data the portion of the interrupted data remaining in the terminal.

7. A digital data communication system according to claim 17, wherein the first and second serial data conductors and the clear-to-send control conductor are parts of a standard RS 232 cable.

8. A digital data communication system according to claim 7, wherein the central processor has a RS 232 standrd serial data port connected to all of the plurality of terminals via the standard RS 232 cable.

9. A digital data communication system for transferring data between a plurality of terminals to a central processor, comprising:

a first serial data conductor connected between the central processor and the plurality of terminals for transferring data to the central processor, said first serial data conductor exclusively transferring serail data to said central processor;

a second serial data conductor connected between the central processor and the plurality of terminals for tranferring data from the central processor, said second serial data conductor exclusively tranferring serial data from said central processor;

a clear-to-send control conductor connected from the central processor to the plurality of terminals for enabling a data transfer between the central processor and one of the plurality of terminals;

request-to-send means for outputting a request-to-send indicator to the central processor enabling the data transfer from the central processor to one of the plurality of terminals;

means for detecting a not-busy condition of the first and second serial data conductors;

means responsvie to the not-busy detecting means for controlling the outputting of data to the central processor from one of the plurality of terminals via the first serial data conductor on a first-come, first-served basis; and

delay means for preventing each terminal from initiating a data transfer for a preselected delay period after the cessation of the busy condition to provide the terminal and the central processor a period to respond to the data transfer therebetween.

10. The digital data communication system according to claim 9, further comprising interference detecting means connected to the first serial data conductor for detecting an interference condition of at least two terminals initiating data transfers to the central processor via the first serial data conductor concurrently.

11. The digital data comprising system according to claim 10, further comprising:

means responsive to the interference detecting means for interrupting the transfer of data from one of the terminals concurrently outputting data onto the first serial data conductor; and

means responsive to the interrupting means for clearing from the terminal interrupted during an interfering transfer of data the portion of the interrupted data remaining within the terminal.

12. A digital data communication system for transferring data between a plurality of terminals to a central processor, comprising:

a first serial data conductor connected between the central processor and the plurality of terminals for transferring data to the central processor, said first serial data conductor exclusively transferring serial data to said central processor;

a second serial data conductor connected between the central processor and the plurality of terminals for tranferring data from the central processor, said second serial data conductor exclusively transferring serial data from said central processor;

a clear-to-send control conductor connected from the central processor to the plurality of terminals for enabling a data transfer between the central processor and one of the plurality of terminals;

request-to-send means for outputting a request-to-send indicator to the central processor enabling the data transfer from the central processor to one of the plurality of terminals;

means for detecting a not-busy condition of the first and second serial data conductors;

means responsive to the not-busy detecting means for controlling the outputting of data to the central processor from one of the plurality of terminals via the first serial data conductor on a first-come, first-served basis;

a plurality of means for detecting a busy condition of the first and second serial data conductors, each located in a respective terminal, for controlling the tansferring of data to the central processor by preventing each terminal not involved in a data transfer from initiating a a data transfer as long as one of the first and second serial data conductors is in a busy condition;

interference detecting means connected to the first serial data conductor for detecting an interference condition of at least two terminals initiating data transfers to the central processor via the first serial data conductor concurrently;

means responsive to the interference detecting means for interrupting the transfer of data from one of the terminals concurrently initiating data transfers to the central processor via the first serial data conductor; and

means responsive to the interrupting means for clearing from the terminal interrupted during an interfering transfer of data the portion of the interrupted data remaining in the terminal.