Method of making an epitaxial gallium arsenide semiconductor wafer using a strained layer superlattice

• US 4,963,508 A
• Filed: 02/22/1990
• Issued: 10/16/1990
• Est. Priority Date: 09/03/1985
• Status: Expired due to Fees

• Current Assignee: Daido Tokushuko Kabushiki Kaisha, Nagoya Institute of Technology
• Original Assignee: Daido Tokushuko Kabushiki Kaisha, Nagoya Institute of Technology
• Inventors: Sakai, Shiro, Umeno, Masayoshi, Yahagi, Shinichiro
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Bunch, William
• Application Number:
  US07/483,364
• Time in Patent Office: 236 Days
• Field of Search: 148/DIG. 25, 148/56, 148/65, 148/72, 148/97, 148/110, 148/160, 148/169, 148/149, 148/33, 148/33.1, 148/33.4, 148/33.5, 156/610-613, 357/16, 357/17, 427/248.1, 427/252, 427/255.1, 437/81, 437/105, 437/107, 437/126, 437/132, 437/108, 437/110, 437/111, 437/133, 437/976
• US Class Current: 117/90
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02461 Phosphides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 31/0693 the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/184 the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
• CPC Class Codes: H01L 33/0066 with a substrate not being a III-V compound
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y10S 117/902 Specified orientation, shape, crystallography, or size of seed or substrate
• CPC Class Codes: Y10S 148/072 Heterojunctions
• CPC Class Codes: Y10S 148/097 Lattice strain and defects
• CPC Class Codes: Y10S 148/16 Superlattice
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization

Abstract

A semiconductor wafer having an epitaxial GaAs layer, including a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100); and at least one intermediate layer epitaxially grown on the major surface of the monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between the Si substrate and the epitaxial GaAs layer which is epitaxially grown on a major surface of the top layer of the at least one intermediate layer. The at least one intermediate layer may comprise one or mor GaP/GaAsP, GaAsP/GaAs superlattice layers. the wafer may be used to produce a seimconductor light emitting element which has a plurality of crystalline gaAs layers including a light emitting layer epitaxially grown on the GaAs layer on the intermediate layer. The wafer may also be used to produce a compound semiconductor device such as amplifying and switching elements, light emitting and receiving elements and photovolataic elements. Methods for producing the semiconductor wafer, light emitting element and compound semiconductor devices are also disclosed.

Claims

1. A method of producing a semiconductor wafer having an epitaxial GaAs layer, comprising the steps of:

preparting a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and

5°

with respect to (100);

forming at least one intermediate layer by epitaxy on said major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said GaAs layer;

said at least one intermediate layer consisting essentially of GaP layer formed on said Si substrate, a GaP/GaAsP superlattice formed on said GAP layer, and a GaAsP/GaAs superlattice on said GaP/GaAsP superlattice, wherein said GaP layer has a greater thickness than the total thickness of said superlattices; and

said GaP/GaAsP superlattice and said GaAsP/GaAs superlattice having an average lattice constant between the lattice constant of said Si substrate and the lattice constant of said GaAs layer; and

forming said epitaxial GaAs layer on said said GaP/GaAsP superlattice.

2. A method of producing a semiconductor wafer, comprising the steps of:

preparing a monocrystalline Si substrate;

forming a GaP layer by epitaxy on a major surface of said monocrystalline Si substrate;

forming at least one GaP/GaAsP superlattice layer by epitaxy on said GaP layer;

forming at least one GaAsP/GaAs superlattice layer by epitaxy on said at least one GaP/GaAsP superlattice layer; and

forming a GaAs layer by epitaxy on said at least one GaAsP/GaAs superlattice layer,

wherein said GaP layer has a greater thickness than the total thickness of said superlattices; and

said GaP/GaAsP superlattice and said GaAsP/GaAs superlattice having an average lattice constant between the lattice constant of said Si substrate and the lattice constant of said GaAs layer.

3. A method according to claim 3, further comprising annealing said monocrystalline Si substrate by subjecting the Si substrate at a temperature between 600°

C. and 1100°

C., to a flow of PH₃ gas for a period ranging from 1 to 60 minutes.