Operational amplifier

• US 4,963,834 A
• Filed: 01/23/1989
• Issued: 10/16/1990
• Est. Priority Date: 01/21/1988
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yukawa, Akira
• Primary Examiner(s): Mottola, Steven
• Application Number:
  US07/299,390
• Time in Patent Office: 631 Days
• Field of Search: 330/252, 330/253, 330/255, 330/257, 330/277, 330/307, 330/310, 330/311
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45012 the addition of two signals being made in a switched capacitor circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45074 A comparator circuit compares the common mode signal to a reference before controlling the differential amplifier or related stages
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 2203/45711 the LC comprising two anti-phase controlled SEPP circuits as output stages, e.g. fully differential
• CPC Class Codes: H03F 3/3032 using two SEPP driving stages
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier

Abstract

An operational amplifier comprises a differential input stage, first and second folded cascode stages connected to the differential input stage, and first and second output inverting amplifiers. The first output inverting amplifier is driven by the output of the first folded cascode stage, and the second output inverting amplifier is driven through a current mirror by the output of the second folded cascode stage, such that a push pull output stage is provided in the operational amplifier. As a result, a driving performance is much improved in regard to a capacitive load, and a range of an output voltage can be expanded equally to a power supply voltage.

Claims

1. An operational amplifier comprising,

a differential input stage to which input terminals are connected,

first and second folded cascode stages connected to said differential input stage, and driven by a common output of said differential input stage,

an inverting amplifier including two transistors, one of said two transistors being connected through a current mirror to said first folded cascade stage, and the other of said two transistors being connected directly to the second folded cascode stage.

an output terminal connected to a connecting point of said two transistors.

2. An operational amplifier comprising,

a constant current source connected to a first power supply line,

a differential transistor pair being a first polarity and connected through source electrodes thereof commonly to said constant current source,

input terminals connected to gate electrodes of said differential transistor pair,

a first folded cascode stage including first and second transistor pairs, said first transistor pair being said first polarity and providing a first current mirror based on said first power supply line, and said second transistor pair being a second polarity and connected through drain electrodes thereof to said first current mirror, through gate electrodes thereof to a reference voltage source, and through source electrodes thereof respectively to drain electrodes of said differential transistor pair,

a second folded cascode stage including third and fourth transistor pairs, said third transistor pair being said first polarity, providing a second current mirror based on said first power supply line, and having a connecting pattern of symmetry relatively to said first current mirror, and said fourth transistor pair being said second polarity and connected through drain electrodes thereof to said second current mirror, through gate electrodes thereof to said reference voltage source, and through source electrodes thereof respectively to said drain electrodes of said differential transistor pair,

a current source transistor pair being said second polarity and connected through drain electrodes thereof to respective ones of said source electrodes of said second and fourth transistor pairs included in said first and second folded cascode stages, and through source electrodes thereof to a second power supply line,

an output transistor pair being said first polarity and connected through drain electrodes thereof to a third current mirror and through gate electrodes thereof respectively to said first and second folded cascode stages, said third current mirror including a transistor pair of said second polarity and based on said second power supply line, and

an output terminal connected to a connecting point between a transistor of said output transistor pair and said third current mirror.

3. An operational amplifier according to claim 2,

wherein said reference voltage source produces first, second and third reference voltages, said first reference voltage being applied to said constant current source, said second reference voltage being applied to said first and second folded cascode stages, and said third reference voltage being applied to said current source transistor pair.

4. An operational amplifier comprising,

a constant current source connected to a first power supply line,

a differential transistor pair being a first polarity and connected through source electrodes thereof commonly to said constant current source,

input terminals connected to gate electrodes of said differential transistor pair,

a first folded cascode stage including first and second transistor pairs, said first transistor pair being said first polarity and providing a first current mirror based on said first power supply line, and said second transistor pair being a second polarity and connected through drain electrodes thereof to said first current mirror, through gate electrodes thereof to a reference voltage source, and through source electrodes thereof respectively to drain electrodes of said differential transistor pair,

a second folded cascode stage including third and fourth transistor pairs, said third transistor pair being said first polarity, providing a second current mirror based on said first power supply line, and having a connecting pattern of symmetry relatively to said first current mirror, and said fourth transistor pair being said second polarity and connected through drain electrodes thereof to said second current mirror, through gate electrodes thereof to said reference voltage source, and through source electrodes thereof respectively to said drain electrodes of said differential transistor pair,

a current source transistor pair being said second polarity and connected through drain electrodes thereof to respective ones of said source electrodes of said second and fourth transistor pairs included in said first and second folded cascode stages, and through source electrodes thereof to a second power supply line,

two transistor pairs each being said first polarity and connected through gate electrodes thereof respectively to said first and second folded cascode stages, and through drain electrodes thereof to a corresponding one of third and fourth current mirrors, said third and fourth current mirrors each including a transistor pair of said second polarity, and

positive and negative output terminals connected to connecting points between said two transistor pairs and said third and fourth current mirrors.