Band rejection filtering arrangement

• US 4,963,945 A
• Filed: 04/07/1989
• Issued: 10/16/1990
• Est. Priority Date: 04/07/1989
• Status: Expired due to Term

• Current Assignee: Gec-Marconi Electronics Systems Corporation
• Original Assignee: Plessey Electronics Systems Corporation
• Inventors: Lebleboojian, Gerald, Cooper, David M.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): URBAN, EDWARD F
• Application Number:
  US07/334,431
• Time in Patent Office: 557 Days
• Field of Search: 455/78, 455/80, 455/81, 455/83, 455/103, 455/119, 455/305, 455/306, 455/307, 333/109, 333/110, 333/115, 333/116
• US Class Current: 455/307
• CPC Class Codes: H01P 1/20 Frequency-selective devices, e.g. filters

Abstract

A band rejection filtering arrangement utilizing bandpass filters each terminated by a matched load. A quadrature hybrid circuit divides the input signals and applies them to the bandpass filters. Signals within the rejection band are dissipated by the filters and matched loads, whereas desired signals are reflected. The reflected signals are then combined by the quadrature hybrid circuit to provide the band rejected output. This arrangement is made switchable between an all pass mode and the band rejection mode by providing PIN diodes between the quadrature hybrid circuit and the bandpass filters.

Claims

1. A band rejection filtering arrangement comprising:

a quadrature hybrid circuit having a first pair of terminals and a second pair of terminals, said first pair of terminals being isolated from each other, said second pair of terminals being isolated from each other, signal transmissions between the first of said first pair of terminals and the first of said second pair of terminals being effected without phase shift, signal transmission between the first of said first pair of terminals and the second of said second pair of terminals being effected with a 90°

phase shift, signal transmission between the second of said first pair of terminals and the second of said second pair of terminals being effected without phase shift, and signal transmission between the second of said first pair of terminals and the first of said second pair of terminals being effected with a 90°

phase shift;

a first bandpass filter having its input coupled to the first of said second pair of terminals;

a second bandpass filter having its input coupled to the second of said second pair of terminals;

a first load coupled to the output of said first bandpass filter;

a second load coupled to the output of said second bandpass filter;

means for providing an input signal at the first of said first pair of terminals; and

means for receiving a signal at the second of said first pair of terminals;

wherein said first and second bandpass filters are tuned to pass the rejection band.

2. The arrangement according to claim 1 wherein said first and second loads are matched to their respective bandpass filters.

3. The arrangement according to claim 1 wherein one of said providing means and said receiving means is a transceiver and the other of said providing means and said receiving means is an antenna.

4. The arrangement according to claim 1 further including switching means for selectively switching said arrangement between an all pass mode and a band rejection mode, said switching means comprising:

first controllable resistance means coupled to the first of said second pair of terminals and said first bandpass filter input;

second controllable resistance means coupled to the second of said second pair of terminals and said second bandpass filter input; and

control means coupled to said first and second controllable resistance means for selectively causing said first and second controllable resistance means to each exhibit either a low resistance characteristic or a high resistance characteristic in order to selectively achieve said all pass mode or said band rejection mode.

5. The arrangement according to claim 4 wherein said first and second controllable resistance means each includes a PIN diode.

6. The arrangement according to claim 5 wherein said control means includes means for controlling the bias polarity of said PIN diodes.

7. The arrangement according to claim 6 wherein each of said PIN diodes is connected in series between a respective one of said second pair of terminals and a bandpass filter input.

8. The arrangement according to claim 7 wherein said control means is operative to forward bias said PIN diodes for said band rejection mode and is operative to reverse bias said PIN diodes for said all pass modes.

9. The arrangement according to claim 6 wherein each of said PIN diodes is connected as a shunt to ground from a respective bandpass filter input.

10. The arrangement according to claim 9 wherein said control means is operative to reverse bias said PIN diodes for said band rejection mode and is operative to forward bias said PIN diodes for said all pass mode.