Harvard architecture microprocessor with arithmetic operations and control tasks for data transfer handled simultaneously

• US 4,964,046 A
• Filed: 12/22/1989
• Issued: 10/16/1990
• Est. Priority Date: 06/02/1987
• Status: Expired due to Term

• Current Assignee: Deutsche ITT Industries GmbH
• Original Assignee: Deutsche ITT Industries GmbH
• Inventors: Winterer, Martin, Mehrgardt, Soenke
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): MILLS, JOHN G
• Application Number:
  US07/453,027
• Time in Patent Office: 298 Days
• Field of Search: 364/200 MS File
• US Class Current: 712/36
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544

Abstract

A central processor for digital signal processing operates at a high clock rate. In the central processor, data is transferred and processed largely in parallel and simultaneously. A buffer is inserted in the data link between a data memory and an ALU by means of at least three data buses so that within one clock period, all necessary data transfers for a two-address operation of the ALU are performed by using the buffer. In particular, a unidirectional data bus and a bidirectional data bus transfer data from the buffer to the ALU, and the bidirectional data bus transfers the result of an ALU operation back to the buffer. Simultaneously with the transfers between the buffer and the ALU, a data transfer is performed between the data memory and the buffer. The data transfers and the data processing are controlled by a control unit in which a fixed program is stored segment by segment. The use of pipelining in the control unit permits a high processing speed. The use of delayed branching is supplemented by the skip technique. The central processor does not utilize interrupt control. Rather, a scheduler selectively changes the sequence in which a program operates in response to an external or internal task request only at the end of the segment currently being executed so that the current program segment is concluded without interruption.

Claims

1. A digital data processor including an arithmetic logic unit ("ALU") that performs data processing operations, said ALU having first and second ALU inputs and an ALU output;

a data memory having a data memory input and a data memory output; and

a control unit connected to the data memory and the ALU by at least one data memory control bus and at least one ALU control bus, respectively, said digital data processor operating in synchronism with a clock signal to provide pipelined data processing operations sin response to pipelined instructions, said digital data processor comprising;

a buffer interposed between the ALU inputs and output and the data memory input and output to transfer data between said ALU and said data memory, said buffer controlled by said control unit via a buffer control bus;

a first bidirectional data link interconnecting the data memory input and output and the buffer, said first bidirectional data link comprising first and second unidirectional data buses on which data flows in opposite directions; and

a second bidirectional data link interconnecting said ALU inputs and output and said buffer, said second bidirectional data link comprising third and fourth unidirectional data buses on which data flows in the direction of the ALU inputs and a fifth unidirectional data bus on which data flows in the direction of the buffer from said ALU output;

wherein during one period of said clock signal, data transfers are performed over said first, second, third, fourth and fifth unidirectional data buses at the same time as said ALU performs said data processing operations, so that data transfers between the buffer and the ALU occur simultaneously with transfers between the buffer and the data memory;

wherein said buffer comprises address-selected memory cells which are switched through on any of the five unidirectional data buses and are read from or written into independent of each other;

wherein said control unit provides to the buffer over the buffer control bus decoded delayed branching instructions and conditional and unconditional skip instructions in a pipelined instruction sequence, said control unit comprising;

a control unit memory which holds an instruction list that is fetchable instruction word by instruction word, wherein an instruction word fetched during a period of said clock signal comprises all data-transfer instructions, control instructions, and ALU-operation instructions to be performed during an associated clock period, said instruction list being divided into segments, each said segment being executed without being interrupted by an interrupt, said instruction words being provided as outputs from said control-unit memory;

an instruction decoder that receives said instruction words from said control unit memory and provides said ALU-operation instructions to control said ALU, said instruction decoder further selectively providing task requests on a task request bus;

a set of task request terminals that receive a set of task requests from a device external to said control unit; and

a scheduler to delay jump instructions connected to said set of task request terminals and to said instruction decoder, said scheduler operating only at the end of one of said segments currently being executed in said instruction list to selectively initiate a jump to the beginning of a selectable different one of said segments in said instruction list in response to task request signals applied to it from said task request terminals or from said instruction decoder.

2. The digital data processor as defined in claim 1, wherein said ALU performs at least one of the following functions on the pipelined data:

addition, right shifting and left shifting;

logic operations in the form of AND operations and exclusive-OR operations; and

inversion of the applied data.

3. The digital data processor as claimed in claim 1, wherein said ALU has at least one switchable direct data bus connected from said ALU output to one of said first and second ALU inputs.