Direct digital synthesizer driven phase lock loop frequency synthesizer
First Claim
1. An apparatus for synthesizing frequencies, comprising:
- variable reference means for generating a periodic signal of a frequency selected from a plurality of reference frequencies, said variable reference means comprising,phase accumulator means for, receiving a digital frequency control signal indicative of a selected phase increment value, receiving an externally generated clock signal, accumulating phase increment values at a rate corresponding to said clock signal, and providing an accumulator output signal corresponding to said accumulated phase increment values;
memory means for storing a plurality of amplitude values each corresponding to a respective accumulated phase increment value, receiving said accumulator output signal and providing a memory output signal indicative of the amplitude value corresponding to each accumulated phase increment value of said accumulator output signal; and
converter means for, receiving said memory output signal converting said received memory output signal to an analog amplitude signal corresponding to said memory output signal amplitude values, and providing said analog amplitude signal as said periodic signal; and
frequency tuning means for receiving said periodic signal and generating an output signal of a frequency which is a multiple of said periodic signal frequency.
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Abstract
A frequency synthesizer which uses a direct digital synthesizer (DDS) to drive a phase lock loop. The DDS generates a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. A phase lock loop receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal.
In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference , the number of bits in the digital word of the frequency control signal and the DDS step size as determined by the frequency control signal. Optional dividers may be provided in the feedback path which may further affect the synthesizer output frequency.
130 Citations
19 Claims
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1. An apparatus for synthesizing frequencies, comprising:
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variable reference means for generating a periodic signal of a frequency selected from a plurality of reference frequencies, said variable reference means comprising, phase accumulator means for, receiving a digital frequency control signal indicative of a selected phase increment value, receiving an externally generated clock signal, accumulating phase increment values at a rate corresponding to said clock signal, and providing an accumulator output signal corresponding to said accumulated phase increment values; memory means for storing a plurality of amplitude values each corresponding to a respective accumulated phase increment value, receiving said accumulator output signal and providing a memory output signal indicative of the amplitude value corresponding to each accumulated phase increment value of said accumulator output signal; and converter means for, receiving said memory output signal converting said received memory output signal to an analog amplitude signal corresponding to said memory output signal amplitude values, and providing said analog amplitude signal as said periodic signal; and frequency tuning means for receiving said periodic signal and generating an output signal of a frequency which is a multiple of said periodic signal frequency. - View Dependent Claims (2, 3, 4, 5)
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6. A frequency synthesizer comprising:
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a direct digital synthesizer (DDS) having, a fine frequency control input and a DDS clock input for respectively receiving externally generated phase data and an externally generated clock signal, and an output at which a reference signal is provided; a filter having an input, coupled to said DDS output, and an output; and a phase lock loop having a loop input coupled to said filter output, a coarse frequency control input for receiving a divide-by-N signal, and a loop output wherein said loop provides at said loop output a synthesizer output signal of a frequency N times the frequency of said reference signal. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A phase lock loop frequency synthesizer comprising:
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a phase detector having a reference input for receiving an externally generated reference signal of a predetermined frequency, a feedback input and an output; a loop filter having an input, coupled to said detector output, and an output; a voltage controlled oscillator having an input, coupled to said loop filter output, and an output for providing a synthesizer output signal; a direct digital synthesizer (DDS) having a DDS clock input coupled to said oscillator output, a frequency control input for receiving externally generated phase data, and an output; and a bandpass filter having an input coupled to said DDS output and an output coupled to said detector feedback input. - View Dependent Claims (13, 14, 15, 16)
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17. A method for synthesizing frequency comprising the steps of:
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providing a direct digital synthesizer (DDS) capable of generating an analog DDS output signal at a frequency selected from a plurality of frequencies; providing externally generated phase data and clock signals to said DDS; generating in said DDS, in response to an input of said phase data and said clock signal, a DDS analog output signal having a frequency corresponding to said phase data; providing a phase lock loop capable of generating a loop output signal at a frequency corresponding to an input reference signal and a divide-by-N signal; providing to said phase lock loop, said DDS output signal as said reference signal, and said divide-by-N signal; and generating in said phase lock loop, in response to said input of said DDS output signal and said divide-by-N signal, said loop output signal corresponding in frequency to a multiple of aid generated DDS output signal. - View Dependent Claims (18, 19)
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Specification