Vertical MOS field effect transistor having a high withstand voltage and a high switching speed

• US 4,965,647 A
• Filed: 05/17/1989
• Issued: 10/23/1990
• Est. Priority Date: 02/16/1987
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Takahashi, Mitsuasa
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US07/355,855
• Time in Patent Office: 524 Days
• Field of Search: 357/23.4, 357/23.8, 357/13
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A V-MOS FET has a semiconductor body of one conductivity type, a plurality of base regions of the other conductivity type formed in a surface portion of the semiconductor body in a form of matrix having rows and columns, a plurality of source regions of the one conductivity type formed in the base regions, a plurality of auxiliary regions of the other conductivity type formed in the surface portion of said semiconductor body at crossing points of the rows and columns of the base region matrix, a mesh-shape gate electrode formed on region between the source regions to cover the auxiliary regions, a source electrode contacting at least the source regions and a drain electrode contacting a back surface of the semiconductor body.

Claims

1. A semiconductor device comprising:

a drain region of one conductivity type which is a semiconductor substrate having a main surface and a back surface;

a plurality of base regions of the other conductivity type formed in said drain region from said main surface;

a plurality of source regions of said one conductivity type formed in said base regions, respectively, to define channel regions at peripheries of said base regions, said channel regions having a first depth;

a plurality of auxiliary regions of said other conductivity type formed in said drain region from said main surface between said base regions, said auxiliary regions being separated from said base regions and having a second depth shallower than said first depth;

a gate insulator film formed on said main surface to cover said auxiliary regions, said channel regions and said drain regions between said auxiliary regions and said channel regions;

a gate electrode formed on said gate insulator film;

a source electrode contacting at least said source regions; and

a drain electrode attached to said base surface of said semiconductor substrate.

2. A semiconductor device as claimed in claim 1 wherein said base regions are arranged in a form of matrix having rows and columns, said auxiliary regions being formed at portions crossing said rows and said columns of said base region matrix.

3. A semiconductor device as claimed in claim 2, wherein said auxiliary regions have a shape of quadrilateral having sides parallel with said rows and columns of said base region matrix.

4. A semiconductor device as claimed in claim 3, wherein respective corners of said auxiliary regions are in a position which has a distance within a half of an interval between parallel opposing base regions from corners of said base region nearest to the respective corners of said auxiliary region.

5. A semiconductor device as claimed in claim 4, wherein said respective corners of said auxiliary regions are separated from the corners of said base region nearest to the respective corners of said auxiliary regions with at least a third of said interval between said parallel opposing base regions.

6. A semiconductor device as claimed in claim 5, wherein said gate electrode has a mesh-shape.