Method of making an integrated, microminiature electric-to-fluidic valve

• US 4,966,646 A
• Filed: 10/26/1988
• Issued: 10/30/1990
• Est. Priority Date: 09/24/1986
• Status: Expired due to Term

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Inventors: Zdeblick, Mark
• Primary Examiner(s): Powell, William A.
• Application Number:
  US07/263,117
• Time in Patent Office: 734 Days
• Field of Search: 156/633, 156/643, 156/644, 156/647, 156/649, 156/651, 156/653, 156/655, 156/656, 156/657, 156/659.1, 156/661.1, 156/662, 156/668, 346/1.1, 346/140 R, 204/15, 29/610.1, 29/613, 29/620, 29/621.1, 251/11, 251/129
• US Class Current: 216/2
• CPC Class Codes: F15C 3/04 using diaphragms using loose plates or foils F15C3/005; connection of valves to inflatable elastic bodies B60C29/00
• CPC Class Codes: F15C 5/00 Manufacture of fluid circuit elements; Manufacture of assemblages of such elements integrated circuits
• CPC Class Codes: F16K 2099/0074 using photolithography, e.g. etching
• CPC Class Codes: F16K 2099/008 Multi-layer fabrications
• CPC Class Codes: F16K 2099/0084 Chemistry or biology, e.g. "lab-on-a-chip" technology
• CPC Class Codes: F16K 2099/009 Fluid power devices
• CPC Class Codes: F16K 99/0001 Microvalves microdevices B81B1/00; manufacture or treatment of devices or systems in or on a substrate B81C1/00; microfluidic structures B01L3/5027; micropumps F04B19/006
• CPC Class Codes: F16K 99/0015 Diaphragm or membrane valves
• CPC Class Codes: F16K 99/0044 using thermo-electric means
• CPC Class Codes: F16K 99/0061 actuated by an expanding gas or liquid volume
• CPC Class Codes: G02B 3/0006 Arrays G02B3/02, G02B5/188 take precedence
• CPC Class Codes: G02B 3/0012 characterised by the manufacturing method
• CPC Class Codes: G02B 3/14 of variable focal length
• CPC Class Codes: G02B 6/3692 with surface micromachining involving etching, e.g. wet or dry etching steps surface micromachining involving subtractive techniques B81C1/00055
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence

Abstract

A method of making an integrated, microminiature, electric-to-fluidic valve. The method comprises, in one embodiment, anisotropically etching a cavity in a silicon wafer to form a thin membrane at the bottom of a trench. Then a second wafer is etched to form an exit path surrounded by a valve seat positioned such that when these two wafers are sandwiched together, the valve seat lies under the membrane. An input passageway joining a manifold cavity formed around the valve seat is then etched in the surface of the second wafer which will mate with the diaphragm side of the first wafer. The two wafers are then bonded together after suitable alignment. A third pyrex wafer is then coated with a resistor material which will be over the cavity in the first wafer when the first and third wafers are bonded together. Conductive leads and wire attach pads are also formed. Finally, a fill hole is etched into the third wafer over the position of the cavity such that the cavity can be filled. The first and third wafers are then bonded together to complete the valve.

Claims

1. A method for manufacturing an apparatus comprising the steps of:

(1) etching a membrane cavity trench using masking material in a first semiconductor wafer having first and second sides with a depth such that a flexible diaphragm is left which is defined by the bottom of the trench and said second side;

(2) etching a nozzle trench in a first side of a second semiconductor wafer having first and second sides using masking material;

(3) making with masking material a sealing surface portion of the second side of said second wafer and etching said second surface back so that when said masking material is removed, said sealing surface projects as a mesa from said second side, said sealing surface being shaped and located so as to have an etched back depression therein located within the perimeter of said nozzle trench as said perimeter is projected onto said second side of said second wafer;

(4) masking a manifold trench portion of said second side of said second wafer without removing said sealing surface masking material and etching said second side of said second wafer back sufficiently to form a manifold trench in said second side around said sealing surface, said etch also being deep enough to etch said second side of said second wafer so as to form a fluid communication path from said depression to said nozzle trench so as to create a nozzle aperture in said sealing surface;

(5) removing all masking material from said second side of said second wafer;

(6) bonding said second side of said second wafer to said second side of said first wafer so that said sealing surface and nozzle aperture are located such if said flexible diaphragm is flexed toward said second wafer far enough, said flexible diaphragm would come to rest on said sealing surface and cut off flow of any material flowing through said nozzle aperture;

(7) filling said membrane cavity trench with a material which has a changing vapor pressure with changing temperature and hermetically sealing said material in said membrane cavity.

2. The method of claim 1 wherein said step 6 further comprises the steps of:

(1) forming a layer of material on said second side of said first wafer before the bonding which is capable of blocking the migration of the metal selected for step 2 below into said semiconductor;

(2) forming a layer of metal having a tendency to diffuse into said semiconductor on top of said migration blocking layer;

(3) placing the second side of the first and second wafers together and bringing the structure to a high enough temperature for a long enough time to cause the metal layer to diffuse into the semiconductor far enough to create a bond.

3. The method of claim 2 wherein step 1 includes the step of forming a layer of oxide tungsten, titanium, or other diffusion barrier on the second side of a silicon, germanium or galium arsenide or other semiconductor first wafer and wherein step 2 includes the step of depositing a layer of aluminum on top of a layer of silicon dioxide.

4. A method of forming an apparatus comprising the steps of:

(1) forming a trench in a first wafer said trench having, at least one flexible wall;

(2) forming a fluid passageway in a second wafer with a sealing surface forming a part of the fluid passageway boundary;

(3) bonding said first and said second wafers together so that said sealing surface and said flexible wall and the walls of said fluid passageway define a portion of said fluid passageway which has a variable cross sectional area which depends upon the position of said flexible wall;

(4) forming a cavity by sealing the opening in said trench as part thereof and encapsulating a fixed volume of a material which changes its vapor pressure with changing temperature in said cavity; and

(5) providing a means for allowing the material trapped in said cavity to be heated above or cooled below the ambient temperature.

5. The method of claim 4 wherein said step of encapsulating a fixed volume of material includes the steps of placing the first wafer in a chamber of the material to be encapsulated and anodically bonding a third wafer over a fill hole into the cavity in said first wafer so as to hermetically seal said fill hole.

6. The method of claim 4 wherein said steps of encapsulating a material in said cavity and providing a means for heating the material in said cavity include the steps of:

etching a pattern of resistive conductor on the surface of a third wafer said pattern being small enough to substantially fit in said trench and having metal leads leading away from said conductive pattern to bonding pads located outside the perimeter of said trench;

in the presence of vacuum, bonding said third wafer to said first wafer with said conductive pattern facing inward and located substantially within said trench, said bond forming substantially a complete seal except for small leakage paths at the sides of said metal leads leading to said bonding pads;

immersing the structure in a chamber containing the liquid to be encapsulated and pressurizing the chamber if necessary to increase the rate of fill of said cavity through said small leaks;

after the cavity has been filled to a user defined extent, attaching the bonding pads and metal leads as the cathode in a metal electroplating system including a bath of electroplating solvent and plating a sufficient amount of metal onto the bonding pads and metal leads so as to plug up the small leakage paths and hermetically seal said cavity.

7. The method of claim 4 wherein the steps of forming said cavity and encapsulating material in said cavity includes the steps of:

bonding a third wafer over the opening of the trench to hermetically seal the trench;

forming a fill hole in said third wafer to allow fluid access to said trench;

filling said cavity with a user defined quantity of the material to be encapsulated through said fill hole;

sealing said fill hole.

8. The method of claim 7 where said fill hole is laser drilled and the filling step includes the step of pressurizing the chamber containing the liquid or gas to be encapsulated.

9. The method of claim 4 wherein the steps of forming said cavity and encapsulating material therein include the steps of anodically bonding a third wafer over the opening of said trench in the presence of the gas, liquid or solid to be encapsulated at a high pressure adequate to control the vapor pressure of the material to be encapsulated and to prevent escape of the material to be encapsulated from the cavity.

10. A method of forming an apparatus comprising the steps of:

etching a trench in a first side of a first wafer;

depositing a spacer layer in said trench;

depositing a layer of polyimide over said spacer layer;

etching away the polyimide lying on the surface of the wafer outside the perimeter of the trench;

etching a trench in a second side of said first safer which is parallel to said first side, said etching of the trench in said second side to continue until the trench exposes at least a portion of said spacer layer;

etching away at least some of said spacer layer to form a polyimide membrane;

encapsulating a fixed volume of material which has a changing vapor pressure with changing temperature in a cavity comprising said trench in said first side having a top placed over said trench and bonded to said first wafer.

11. The method of claim 10 wherein said trench in said first side has at least one stair step or discontinuity in the side walls thereof such that the polyimide membrane formed using the walls of the trench as a mold has a fold in it like a bellows fold.

12. The method of claim 10 wherein said step of encapsulating comprises the steps of etching a resistor pattern in a layer of conductive material deposited on the surface of a second wafer and anodically bonding the second wafer to said first wafer in the presence of the material to be encapsulated so that the resistor pattern is in the cavity formed by the trench and said second wafer.

13. The method of claim 10 wherein said step of encapsulating comprises the steps of etching a resistor pattern in a layer of conductive material deposited on the surface of a second wafer having metal leads extending to bonding pads at some user defined distance from said resistor pattern and bonding the second wafer to said first wafer in a vacuum so that the resistor pattern is in the cavity formed by the trench and said second wafer and said cavity is evacuated and sc that a substantial seal except for small leakage paths at the sides of said metal leads, and then immersing the structure in the material to be encapsulated and pressurizing the system until a user defined amount of material has leaked into said cavity, and then connecting the metal leads as the cathode in an electroplating bath and plating a sufficient amount of metal on said metal leads to hermetically seal said cavity by blocking said leakage paths.

14. The method of claim 11 wherein said step of encapsulating comprises the steps of etching a resistor pattern in a layer of conductive material deposited on the surface of a second wafer and anodically bonding the second wafer to said first wafer in the presence of the material to be encapsulated so that the resistor pattern is in the cavity formed by the trench and said second wafer.

15. The method of claim 11 wherein said step of encapsulating comprises the steps of etching a resistor pattern in a layer of conductive material deposited on the surface of a second wafer having metal leads extending to bonding pads at some user defined distance from said resistor pattern and bonding the second wafer to said first wafer in a vacuum so that the resistor pattern is in the cavity formed by the trench and said second wafer and said cavity is evacuated and so that a substantial seal except for small leakage paths at the sides of said metal leads, and then immersing the structure in the material to be encapsulated and pressurizing the system until a user defined amount of material has leaked into said cavity and then connecting the metal leads as the cathode in an electroplating bath and plating a sufficient amount of metal on said metal leads to hermetically seal said cavity by blocking said leakage paths.

16. The method of claim 10 wherein the step of encapsulating comprises the steps of forming a cavity by bonding a second wafer over the first wafer so as ;

o hermetically seal said trench and then forming a fill hole in said second wafer to provide fluid access to said cavity, filling said cavity through said fill hole and sealing said fill hole.

17. The method of claim 16 wherein said fill hole is formed by laser drilling and wherein the step of filling said cavity comprises the steps of evacuating said cavity and immersing the structure in the material to be encapsulated until the cavity is at least partially full.