Trench power MOSFET device

• US 4,967,245 A
• Filed: 03/14/1988
• Issued: 10/30/1990
• Est. Priority Date: 03/14/1988
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Thornton, Neill R., Cogan, Adrian I.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US07/167,617
• Time in Patent Office: 960 Days
• Field of Search: 357/23.4, 357/55, 357/59 G, 357/49, 437/73, 437/79, 437/203
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench power MOSFET device is disclosed wherein the method of manufacturing produces a high density MOSFET cell with good breakdown characteristics.

Claims

1. A high cell density product for power MOSFETS, the product being produced by the following method:

providing a heavily doped substrate, of first conductivity type, having a top surface;

providing a first layer of lightly doped material of first conductivity type on top of and contiguous to the substrate;

providing a second layer of second conductivity type opposite to the first conductivity type, on top of and contiguous to the first layer, with the first layer being positioned between the substrate and the second layer;

providing a third layer of heavily doped material, of first conductivity type, on top of and contiguous to the second layer, with second layer being positioned between the first layer and the third layer;

producing a substantially rectangular or trapezoidal groove in the combined first layer/second layer/third layer that reaches through all of a transverse section of the second layer, and reaches through a portion but not all of a transverse section of the first layer and exposes a bottom wall and said walls of the groove;

providing a thick oxide layer inside the groove covering the bottom wall of the groove;

providing a thin oxide layer inside the groove covering all side walls of the groove;

providing polysilicon that fills the groove;

providing a covering layer of substantially undoped oxide material that selectively covers the polysilicon at the top of the groove and immediately adjacent to the groove boundary at the top surface thereof so that no part of the polysilicon in the groove is exposed;

removing substantially all of the third layer except a small region adjacent the thin oxide layer, so that a surface of the second layer is exposed; and

providing a metallized layer of material covering and contiguous to the top surface of the second layer, the tip of the groove and all polysilicon material adjacent to the boundary of the groove.

2. A structure for providing power MOSFETs of high cell density, the structure comprising:

a heavily doped substrate of semiconductor material of first conductivity type having a top surface;

a first covering layer of lightly doped semiconductor material of first conductivity type, positioned on top of and contiguous to the substrate and having a top surface;

a second covering layer of semiconductor material of second conductivity type opposite to the first conductivity type, positioned on top of and contiguous to the first covering layer and having a top surface;

a substantially rectangular or trapezoidal shaped groove that extends substantially vertically from the top surface of the second covering layer through all of a transverse section of the second covering layer and through a portion but not all of a transverse section of the first covering layer, the groove having a bottom wall and side walls;

a thick oxide layer positioned inside the groove and contiguous to the bottom wall of the groove;

an oxide layer positioned inside the groove and contiguous to and completely covering the side walls of the groove, where the thickness of this oxide layer is less than the thickness of the oxide layer that is contiguous to the bottom wall of the groove;

doped polysilicon having a top surface and positioned within and filling the remainder of the groove so that the top surface of the polysilicon extends above the top surface of the second covering layer;

a second thick oxide layer positioned on top of the polysilicon and extending beyond the sides thereof, so that, together with the oxide layer covering the side walls, the polysilicon is electrically isolated from the first and second covering layers;

a source region semiconductor material of heavily doped first conductivity type, positioned on top of a portion of the second covering layer adjacent to the side walls of the groove and adjacent to the second thick oxide layer; and

a third covering layer of electrically conducting material covering and contiguous to the source region, the second thick oxide layer and the top surface of the second covering layer.

3. A structure according to claim 2, wherein said electrically conducting material of said third covering layer is a metal.

4. A structure according to claim 2, wherein said first thick oxide layer positioned at said bottom wall of said groove includes oxygen placed there by ion implantation.