Semiconductor device having field effect transistors
First Claim
1. A semiconductor device having an array of elemental cells, each of said elemental cells comprising:
- a semiconductor substrate having a main surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type positioned opposed to the first semiconductor region, and a trench formed in said semiconductor substrate, wherein a portion of side wall surface of said trench includes exposed surfaces of said first and second semiconductor regions;
first and second impurity regions of the second conductivity type formed spaced apart from each other in said first semiconductor region, said first and second impurity regions defining in said first semiconductor region a first channel region including said exposed surface of said first semiconductor region;
a first gate insulating layer formed in said trench on said exposed surface of the first semiconductor region of said first channel region;
a first gate electrode formed in said trench on said first gate insulating layer;
third and fourth impurity regions of the first conductivity type formed spaced apart from each other in said semiconductor region, said third and fourth impurity regions defining in said second semiconductor region a second channel region including said exposed surface of said second semiconductor region;
a second gate insulating layer formed in said trench on said exposed surface of said second semiconductor region of said second channel region; and
a second gate electrode formed in said trench on said second gate insulating layer.
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Accused Products
Abstract
A semiconductor device having field effect transistors (FETs) is provided. In the FET, a channel surface where a channel region and a gate electrode are opposed to each other is formed approximately vertical to a main surface of a substrate. A p type (n type) semiconductor region is formed on the main surface of the substrate, and a concave portion with a portion of side wall surfaces thereof being an exposed surface of the semiconductor region is formed. In the semiconductor region, n type (p type) drain and source regions are formed spaced apart from each other defining the channel region. A gate insulating layer is formed in the concave portion on the exposed surface of the semiconductor region on the channel region. A gate electrode is formed on the gate insulating layer in the concave portion. Consequently, the rate of the area occupied by one field effect transistor to the main surface of the substrate can be reduced. Therefore, a semiconductor device can be provided in which field effect transistors are integrated to a high degree without reducing channel length and without degrading performance of the transistors.
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Citations
9 Claims
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1. A semiconductor device having an array of elemental cells, each of said elemental cells comprising:
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a semiconductor substrate having a main surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type positioned opposed to the first semiconductor region, and a trench formed in said semiconductor substrate, wherein a portion of side wall surface of said trench includes exposed surfaces of said first and second semiconductor regions;
first and second impurity regions of the second conductivity type formed spaced apart from each other in said first semiconductor region, said first and second impurity regions defining in said first semiconductor region a first channel region including said exposed surface of said first semiconductor region;a first gate insulating layer formed in said trench on said exposed surface of the first semiconductor region of said first channel region; a first gate electrode formed in said trench on said first gate insulating layer; third and fourth impurity regions of the first conductivity type formed spaced apart from each other in said semiconductor region, said third and fourth impurity regions defining in said second semiconductor region a second channel region including said exposed surface of said second semiconductor region; a second gate insulating layer formed in said trench on said exposed surface of said second semiconductor region of said second channel region; and a second gate electrode formed in said trench on said second gate insulating layer. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device having an array of elemental cells, each of said elemental cells comprising:
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a semiconductor substrate having a main surface; a first semiconductor region of a first conductivity type and a first trench formed in said semiconductor substrate, wherein a portion of side wall surfaces of said first trench includes an exposed surface of said first semiconductor region; first and second impurity regions of a second conductivity type formed spaced apart from each other in said first semiconductor region, said first and second impurity regions defining a first channel region in said first semiconductor region including said exposed surface of said first semiconductor region; a first gate insulating layer formed in said first trench on said exposed surface of said first semiconductor region of said first channel region; a first gate electrode formed in said first trench on said first gate insulating layer; a second semiconductor region of the first conductivity type, a first side of said second semiconductor region being positioned approximately parallel to said first semiconductor region, a third semiconductor region of the second conductivity type positioned opposed to a second side of said second semiconductor region which is opposite from said first side, and a second trench formed in said semiconductor substrate, wherein a portion of side wall surface of said second trench includes exposed surfaces of said second and third semiconductor regions; third and fourth impurity regions of the second conductivity type formed spaced apart from each other in said second semiconductor region, said third and fourth impurity regions defining in said second semiconductor region a second channel region including said exposed surface of said second semiconductor region; a second gate insulating layer formed in said second trench on said exposed surface of the second semiconductor region of said second channel region; a second gate electrode formed in said second trench on said second gate insulating layer; fifth and sixth impurity regions of the first conductivity type formed spaced apart from each other in said third semiconductor region, said fifth and sixth impurity regions defining in said third semiconductor region a third channel region including said exposed surface of said third semiconductor region; a third gate insulating layer formed in said concave portion on said exposed surface of said third semiconductor region of said third channel region; and a third gate electrode formed in said second trench on said third gate insulating layer; wherein first, second and third channel surfaces for respectively defining a magnitude of a carrier path in said first, second and third channel regions are formed in planes that are approximately perpendicular to the main surface of said semiconductor substrate. - View Dependent Claims (7, 8, 9)
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Specification