Structure for use in self-biasing and source bypassing a packaged, field-effect transistor and method for making same

• US 4,967,258 A
• Filed: 03/02/1989
• Issued: 10/30/1990
• Est. Priority Date: 03/02/1989
• Status: Expired due to Fees

• Current Assignee: Ball Corporation
• Original Assignee: Ball Corporation
• Inventors: Fithian, Michael J., Foster, James E.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/319,367
• Time in Patent Office: 607 Days
• Field of Search: 357/51, 357/68, 357/74, 357/80
• US Class Current: 257/533
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/916 Narrow band gap semiconductor material, <<1ev

Abstract

The present invention provides a structure for use in self-biasing and source bypassing a packaged, field-effect transistor (FET) having first and second leads. The structure is readily assembled and provides an excellent noise figure.

Claims

1. A self-biased and source bypassed, packaged, field-effect transistor structure, comprising:

a packaged, field-effect transistor including a housing having a defined width, a field-effect transistor located within said housing, and first and second source leads extending from said field-effect transistor, through said housing, and outward from said housing;

means for grounding, wherein at least a portion of said housing is located intermediate said packaged, field-effect transistor and said means for grounding;

a source resistor for use in biasing the field-effect transistor, said source resistor having a first terminal electrically contacting said means for grounding and a second terminal electrically contacting at least one of the source leads;

a first capacitor for use in grounding the first source lead of the field-effect transistor during AC operation, said first capacitor having a first lower plate electrically contacting said means for grounding and a first upper plate separated from said first lower plate by a first dielectric, wherein said first upper plate of said first capacitor is positioned adjacent to the first source lead of the packaged, field-effect transistor for direct electrical connection therewith;

a second capacitor for use in grounding the second source lead of the field-effect transistor during AC operation, said second capacitor have a second lower plate electrically contacting said means for grounding and a second upper plate separated from said second lower plate by a second dielectric, wherein said second upper plate of said second capacitor is positioned adjacent to the second source lead of the packaged, field-effect transistor for direct electrical connection therewith.

2. A structure, as claimed in claim 1, wherein:

said first upper plate of said first capacitor and said second upper plate of said second capacitor are substantially coplanar.

3. A structure, as claimed in claim 1, wherein:

said means for grounding includes a substantially planar surface for electrically contacting said first lower plate of said first capacitor and said second lower plate of said second capacitor.

4. A structure, as claimed in claim 3, wherein:

said first lower plate of said first capacitor is separated from said first upper plate by a defined distance and said second lower plate of said second capacitor is separated from said second upper plate by said defined distance.

5. A structure, as claimed in claim 2, wherein:

said means for grounding includes a connector for electrically connecting said means for grounding and said first terminal of said resistor, said connector having a first end for electrically contacting said means for grounding and a second end for electrically contacting said first terminal of said resistor, wherein said second end is substantially coplanar with said first upper plate of said first capacitor.

6. A structure, as claimed in claim 5, wherein:

a portion of said connector is operatively attached to at least one of the following;

said first dielectric and said second dielectric.

7. A structure, as claimed in claim 5, wherein:

said first dielectric is the same as said second dielectric and a portion of said connector is operatively attached to said dielectric.

8. A structure, as claimed in claim 5, wherein:

said first terminal of said resistor electrically contacts said second end of said connector and said second terminal of said resistor electrically contacts said first upper plate of said first capacitor.

9. A structure, as claimed in claim 8, wherein said resistor is a chip resistor.

10. A structure, as claimed in claim 3, wherein:

said means for grounding includes a connector for electrically connecting said substantially planar surface and said first terminal of said resistor, said connector having a first end for electrically contacting said substantially planar surface and a second end for electrically contacting said first terminal of said resistor, wherein said second end is substantially coplanar with said first upper plate of said first capacitor.

11. A structure, as claimed in claim 10, wherein:

a portion of said connector is operatively attached to at least one of the following;

said first dielectric and said second dieletric.

12. A structure, as claimed in claim 10, wherein:

said first dielectric is the same as said second dielectric and a portion of said connector is operatively attached to said dielectric.

13. A structure, as claimed in claim 10, wherein:

said first terminal of said resistor electrically contacts said second end of said connector and said second terminal of said resistor electrically contacts said said first upper plate of said first capacitor.

14. A structure, as claimed in claim 13, wherein said resistor is a chip resistor.

15. A structure, as claimed in claim 1, wherein:

said means for grounding includes a first substantially planar land for electrically contacting said first lower plate of said first capacitor and a second substantially planar land for electrically contacting said second lower plate of said second capacitor, a ground plane separated from said first and second lands by a substrate and a first ground pin connecting said first land to said ground plane and a second ground pin connecting said second land to said ground plane.

16. A structure, as claimed in claim 1, wherein:

said first dielectric is the same as said second dielectric.

17. A structure, as claimed in claim 1, wherein:

said means for grounding having a hole located intermediate said first lower plate of said first capacitor and said second lower plate of said second capacitor to reduce capacitive coupling between the field-effect transistor and said means for grounding.

18. A structure, as claimed in claim 1, wherein:

said first capacitor and said second capacitor are separated by at least the width of the housing at the point where the first and second source leads extend outward from the housing.

19. A structure, as claimed in claim 1, wherein:

said first upper plate of said first capacitor and said second upper plate of said second capacitor are positioned to contact said first source lead and said second source lead, respectively, outside of, and immediately adjacent to, a cylinder defined by a periphery of said housing.

20. A self-biased and source bypassed, packaged, field-effect transistor structure, comprising:

a packaged, field-effect transistor including a housing, a field-effect transistor located within said housing, and first and second source leads extending from said field-effect transistor, through said housing, and outward from said housing;

a grounding structure including a first substantially planar land, a second substantially planar land, a grounding plane spaced from said first and second land by a substrate, a first grounding pin electrically connecting said first land and said grounding plane, a second grounding pin electrically connecting said second land and said grounding plane, and a hole located intermediate said first and second lands, wherein at least a portion of said housing is located intermediate said field-effect transistor and said means for grounding;

a first capacitor for use in grounding the first source lead of the field-effect transistor during AC operation, said first capacitor having a first lower plate electrically contacting said first land and a first upper plate separated from said first lower plate by a first dielectric, said first dielectric having a first edge, said first upper plate and said first lower plate separated by a defined distance;

a second capacitor for use in grounding the second source lead of the field-effect transistor during AC operation, said second capacitor having a second lower plate electrically contacting said second land and a second upper plate separated from said second lower plate by said second dielectric, said second upper plate and said second lower plate separated by said defined distance;

a wrap-around connector including a first portion electrically contacting said first land, a second portion spaced from said first portion by said first dielectric and said defined distance, and a third portion extending along said first edge of said first dielectric and electrically connecting said first portion and said second portion, wherein said first upper plate of said first capacitor, said second upper plate of said second capacitor and said second portion of said wrap-around connector are substantially coplanar; and

a chip resistor having a first terminal electrically contacting said second portion of said wrap-around connector and a second terminal electrically contacting said first upper plate of said first capacitor.

21. A self-biased and source bypassed, packaged, field-effect transistor assembly for operation in the microwave range extending from approximately 1 GHz to 12 GHz, comprising:

a packaged, field-effect transistor including a housing, a field-effect transistor located inside said housing, and first and second source leads extending from said field-effect transistor, through said housing, and outward from said housing;

means for grounding, wherein at least a portion of said housing is located intermediate said field-effect transistor and said means for grounding;

a source resistor for use in biasing the field-effect transistor, said source resistor having a first terminal electrically contacting said means for grounding and a second terminal electrically contacting at least one of the source leads;

a first capacitor for use in grounding the first source lead of the field-effect transistor during AC operation, said first capacitor having a first lower plate electrically contacting said means for grounding and a first upper plate separated from said first lower plate by a first dielectric, wherein said first upper plate of said first capacitor is positioned immediately adjacent to the first source lead of the packaged, field-effect transistor for direct electrical connection therewith;

a second capacitor for use in grounding the second source lead of the field-effect transistor during AC operation, said second capacitor having a second lower plate electrically contacting said means for grounding and a second upper plate separated from said second lower plate by a second dielectric, wherein said second upper plate of said second capacitor is positioned immediately adjacent to the second source lead of the packaged, field-effect transistor for direct electrical connection therewith.

22. A self-biased and source bypassed packaged, field-effect transistor assembly, as claimed in claim 21, wherein:

said first source lead is in direct overlapping contact with said first upper plate of said first capacitor and said second source lead is in direct overlapping contact with said second upper plate of said second capacitor.

23. A self-biased and source bypassed packaged, field-effect transistor assembly, as claimed in claim 21, wherein:

said first upper plate of said first capacitor and said second upper plate of said second capacitor are substantially coplanar.

24. A self-biased and source bypassed packaged, field-effect transistor assembly, as claimed in claim 21, wherein:

said first source lead and said first upper plate are substantially parallel and said second source lead and said second upper plate are substantially parallel.

25. A self-biased and source bypassed packaged, field-effect transistor assembly, as claimed in claim 21, wherein:

said field-effect transistor is a gallium-arsenide, field-effect transistor.