Image data conversion device

• US 4,967,274 A
• Filed: 06/03/1988
• Issued: 10/30/1990
• Est. Priority Date: 06/09/1987
• Status: Expired due to Term

• Current Assignee: Fujifilm Corporation (Fujifilm Holdings Corporation)
• Original Assignee: Fuji Photo Film Co Limited (Fujifilm Holdings Corporation)
• Inventors: Sonoda, Fumihiro
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US07/203,839
• Time in Patent Office: 879 Days
• Field of Search: 358/160, 358/22, 364/521
• US Class Current: 348/719
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G09G 1/02 Storage circuits G09G1/06 - G09G1/28 take precedence
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

In an image data conversion device having an image data memory for storing and outputting picture element data to provide reproduced images according to a DMA transmission system, address output means provides address data to specify memory addresses in the image data memory means in a predetermined order. Conversion means, in response, applies to a memory address to the image data memory means which may be different from the memory address specified by the address data, so that, for instance, the addresses of picture element data are directly changed in the DMA transmission.

Claims

1. An image processing system comprising a CPU and an image data conversion device which, while operating in a DMA transmission mode, can effect various image data conversions, said image data conversion device comprising:

image data memory means for storing picture element data and for outputting stored element data in response to a memory address signal;

a data bus for transmitting program address conversion data from the CPU only during a CPU program transmission mode and for receiving stored picture element data outputted from said image data memory means only during the DMA transmission mode, stored picture element data outputted by said image data memory means via said data bus during the DMA transmission mode representing a reproduced image;

address output means for providing address data specifying memory addresses in said image data memory means in a predetermined order; and

conversion means coupled to said data bus for receiving program address conversion data during the CPU program transmission mode, said conversion means being selectively programmed according to the received program address conversion data for each operation in a DMA transmission mode, to effect, while operating in a DMA transmission mode, desired memory address conversions, said programmed conversion means supplying, during the DMA transmission mode and in response to address data provided by said address output means, a memory address which is different from the memory address specified by said address data to effect a desired image data conversion in accordance with the received program address conversion data.

2. A system as claimed in claim 1, in which said address output means provides a plurality of address data specifying picture element data corresponding to one horizontal scan of an image frame.

3. A system as claimed in claim 1, in which said conversion means comprises:

conversion address memory means selectively programmed with conversion address data via said data bus for each operation in a DMA transmission mode, to effect, while operating in a DMA transmission mode, desired memory address conversions, for providing conversion address data in response to address data provided by said address output means, said conversion address data addressing a memory address which is different from the memory address specified by said address data;

base address register means selectively programmed with integer data supplied via said data bus during the CPU program transmission mode for each operation in a DMA transmission mode; and

adding means for adding said conversion address data and said integer data and applying the sum to said image data memory means.

4. A system as claimed in claim 3, wherein the picture element data stored in said image data memory means represents a scanned input picture image signal, and wherein said integer data represents a horizontal scan line of the scanned input picture image signal.

5. A system as claimed in claim 3, wherein said base address register means comprises a plurality of registers each storing a part of a base address for use during an operation of said device in either a memory mode in which picture element data is loaded into said image data memory means or an output mode in which stored picture element data is read from said image data memory means, and data selector means for selecting outputs of said registers for application to said adding means.

6. A system as claimed in claim 3, further including a data bus coupled to said base address register means for loading said registers, coupled to said conversion address memory means for loading said conversion address data, and coupled to said image data memory means for input/output of image data.

7. An image processing system comprising a CPU and a data conversion device which, while operating in a DMA transmission mode, can effect various image data conversions, said image data conversion device comprising:

image data memory means for storing picture element data;

a data bus for transmitting program address conversion data from the CPU during a CPU program transmission mode, and for outputting stored picture element data from said image data memory means during the DMA transmission mode, stored picture element data outputted by said image data memory means representing a reproduced image;

address output means for providing address data specifying memory addresses in said image data memory means in a predetermined order;

conversion means coupled to said data bus for receiving program address conversion data during the CPU program transmission mode, said conversion means being selectively programmed according to the received program address conversion data for each operation in a DMA transmission mode, to effect, while operating in a DMA transmission mode, desired memory address conversion, said programmed conversion means supplying, during the DMA transmission mode and in response to address data provided by said address output means, a memory address which is different from the memory address specified by said address data to effect a desired image data conversion in accordance with the received address conversion data, said conversion means including conversion address memory means for storing, in advance, one of predetermined conversion address data and arbitrary conversion address data.

8. An image processing system comprising a CPU and a data conversion device which, while operating in a DMA transmission mode, can effect various image data conversions, said image data conversion device comprising:

image data memory means for storing picture element data;

a data bus for transmitting program address conversion data from the CPU during a CPU program transmission mode and for outputting stored picture element data from the image data memory means during the DMA transmission mode, stored picture element data outputted by said image data memory means representing a reproduced image;

address output means for providing address data specifying memory addresses in said image data memory means in a predetermined order;

conversion means coupled to said data bus for receiving program address conversion data during the CPU program transmission mode, said conversion means being selectively programmed according to the received program address conversion data for each operation in a DMA transmission mode, to effect, while operating in a DMA transmission mode, desired memory address conversions, said programmed conversion means supplying, in response to address data provided by said address output means, a memory address which is different from the memory address specified by said address data to effect a desired image data conversion in accordance with the received address conversion data; and

a switching means for selecting one of address data from the address output means and converted address data from the conversion means to supply an output signal to the image data memory means.