Adaptive processing system having an array of individually configurable processing components
First Claim
1. A random access processor for real-time signal processing of an input signal, comprising an array having at least first and second contiguous processing elements, each of said processing elements including:
- first, second and third programmable switches, said first programmable switch of said second processing element slaved to said third programmable switch of said first processing element,a multiplier having a first input connected to an output of said first programmable switch, a second input and an output;
a latch having an input connected to an output of said second programmable switch and an output connected to said second input of said multiplier;
an adder having a first input connected to said output of said multiplier, a second input connected to an output of said second programmable switch, and an output connected to an input of said third programmable switch; and
a programmable delay element having an input connected to an output of said first programmable switch, a control terminal for receiving data for setting an amount of delay provided by said programmable delay element, and an output.
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Abstract
An adaptive processing system for real-time signal processing of one or more input signals in parallel-pipeline fashion is provided. According to the invention, the adaptive processing system includes a random access processor having an array of processing elements each being individually configurable. A man-machine interface receives instructions defining how an input signal is to be processed by the random access processor. A configuration controller responsive to the interface is used to generate configuration data defining a configuration of the random access processor, and data flow between contiguous processing elements thereof, for enabling processing of the input signals according to the insructions. The random access processor is configurable into one or more individually addressable processing arrays which may perform linear or nonlinear operations on an input signal.
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Citations
33 Claims
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1. A random access processor for real-time signal processing of an input signal, comprising an array having at least first and second contiguous processing elements, each of said processing elements including:
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first, second and third programmable switches, said first programmable switch of said second processing element slaved to said third programmable switch of said first processing element, a multiplier having a first input connected to an output of said first programmable switch, a second input and an output; a latch having an input connected to an output of said second programmable switch and an output connected to said second input of said multiplier; an adder having a first input connected to said output of said multiplier, a second input connected to an output of said second programmable switch, and an output connected to an input of said third programmable switch; and a programmable delay element having an input connected to an output of said first programmable switch, a control terminal for receiving data for setting an amount of delay provided by said programmable delay element, and an output.
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2. An adaptive systolic array processing system for real-time signal processing of one or more input signals, comprising:
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a random access processor having an array of individually addressable processing elements that are contiguously arranged to process one or more inputs in a parallel-pipeline fashion, in which signals from processing elements are rhythmically clocked into adjacent processing elements through certain interconnected terminals of said processing elements, said processing element having a plurality of said terminals and a plurality of switches whereby said terminals may be selectively coupled internally to other terminals by operating said switches; configuration control means coupled to each of said processing elements to dynamically configure said processing elements by selectively operating said switches. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An adaptive processing system for real-time signal processing of one or more input signals in parallel-pipeline fashion, comprising:
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an array of a plurality of individually addressable and configurable processing elements for receiving and processing said input signals, each processing element having a plurality of programmable switches and wherein selected programmable switches of adjacent processing elements are slave to each other, said processing elements contiguously arranged for data flow between elements for linear and non-linear operations; interface means for inputting instructions defining the processing configuration of the individually configurable processing elements; configuration control means coupled to said processing elements and said interface means and responsive to said interface means for generating configuration data defining the configuration of each element switch of said array to control data flow within and between contiguous processing elements thereof to enable processing of said input signal(s) by said processing elements according to the input instructions; and memory elements connected between said control means and said processing elements. - View Dependent Claims (15, 16, 17, 18, 19)
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20. An adaptive processing system for real-time signal processing of one or more input signals in parallel-pipeline fashion, comprising:
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a random access processor having an array of processing elements individually addressable and internally configurable for receiving and performing the parallel-pipeline processing of the one or more input signals; a man-machine interface for inputting instructions defining the processing configuration of the individually configurable processing elements; a signal data base connected to the man-machine interface for storing a set of all signal parameters processable by the system; a compiler coupled to the signal data base and responsive to the instructions from the man-machine interface for interpreting the instructions in terms of the signal parameters stored in the signal database and, in response thereto, for generating configuration signals for the array necessary to estimate unknown or unspecified signal parameters in the one or more input signals; a central processing unit responsive to the configuration signals from said compiler for generating configuration data defining the internal configuration of the elements of said array and coupling the configuration data to the random access processor for controlling data for flow within and between contiguous processing elements thereof to enable processing of the one or more input signals by the random access processor according to the input instructions; a multi-port random access memory (RAM) connected to the random access processor for providing storage for the central processing unit and a signal path bus for the one or more input signals to and from the random access processor; and a first parallel interface circuit connected to said multi-port RAM for receiving said one or more input signals and for providing pre-processing of said input signals. - View Dependent Claims (21, 22, 23, 24)
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- 25. A random access processor for processing signals at high data rates comprising a systolic array of contiguously arranged processing elements, the processing elements coupled such that signals are clocked from one processing element into an adjacent processing element in a parallel-pipeline fashion, each processing element including programmable means for dynamically configuring a coupling of a signal input of the processing element, a signal output of the processing element, means for adding and means for multiplying, the configuration determining a processing function carried out by the processing element.
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31. A means for dynamically configuring a systolic array of processing elements for real-time digital signal processing of input signals with linear and nonlinear operation, comprising:
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means for individually configuring a processing structure of each processing element in a systolic array of processing elements, the processing elements coupled for parallel-pipeline processing of digital signals with linear and non-linear operations, where a configuration of the structure of each of the processing element in the systolic array determines the operation performed by the systolic array; memory means for transmitting to each processing element in the systolic array an input signal and for receiving from each processing element an output signal. - View Dependent Claims (32, 33)
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Specification