Adaptive processing system having an array of individually configurable processing components

• US 4,967,340 A
• Filed: 11/18/1988
• Issued: 10/30/1990
• Est. Priority Date: 06/12/1985
• Status: Expired due to Fees

• Current Assignee: E-Systems Incorporated (Rtx Corporation)
• Original Assignee: E-Systems Incorporated (Rtx Corporation)
• Inventors: Dawes, Robert L.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/273,155
• Time in Patent Office: 711 Days
• Field of Search: 364/200, 364/900, 364/728
• US Class Current: 712/19
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses

Abstract

An adaptive processing system for real-time signal processing of one or more input signals in parallel-pipeline fashion is provided. According to the invention, the adaptive processing system includes a random access processor having an array of processing elements each being individually configurable. A man-machine interface receives instructions defining how an input signal is to be processed by the random access processor. A configuration controller responsive to the interface is used to generate configuration data defining a configuration of the random access processor, and data flow between contiguous processing elements thereof, for enabling processing of the input signals according to the insructions. The random access processor is configurable into one or more individually addressable processing arrays which may perform linear or nonlinear operations on an input signal.

Claims

1. A random access processor for real-time signal processing of an input signal, comprising an array having at least first and second contiguous processing elements, each of said processing elements including:

first, second and third programmable switches, said first programmable switch of said second processing element slaved to said third programmable switch of said first processing element,

a multiplier having a first input connected to an output of said first programmable switch, a second input and an output;

a latch having an input connected to an output of said second programmable switch and an output connected to said second input of said multiplier;

an adder having a first input connected to said output of said multiplier, a second input connected to an output of said second programmable switch, and an output connected to an input of said third programmable switch; and

a programmable delay element having an input connected to an output of said first programmable switch, a control terminal for receiving data for setting an amount of delay provided by said programmable delay element, and an output.

2. An adaptive systolic array processing system for real-time signal processing of one or more input signals, comprising:

a random access processor having an array of individually addressable processing elements that are contiguously arranged to process one or more inputs in a parallel-pipeline fashion, in which signals from processing elements are rhythmically clocked into adjacent processing elements through certain interconnected terminals of said processing elements, said processing element having a plurality of said terminals and a plurality of switches whereby said terminals may be selectively coupled internally to other terminals by operating said switches;

configuration control means coupled to each of said processing elements to dynamically configure said processing elements by selectively operating said switches.

3. The adaptive processing system as described in claim 2, further including memory means connected to certain of said terminals of each of said processing elements.

4. The adaptive processing system as described in claim 3, wherein said configuration control means comprises signal database means for storing a set of all signal parameters for signals that may be processed by said system.

5. The adaptive processing system as described in claim 4, further including interface means for inputting instructions defining how said input signal is to be processed by said array.

6. The adaptive processing system as described in claim 5, wherein said configuration control means further comprises a compiler coupled to said signal database means and said interface means to interpret instructions from said interface means in terms of the set of all signal parameters stored in said signal database, to determine the operations to be performed by said random access processor and the necessary configuration data, and, if necessary, determining configuration data necessary to ascertain unknown or unspecified signal parameters to carry out said instructions.

7. The adaptive processing system as described in claim 6, wherein said configuration control means further comprises a central processing unit coupled to said processing elements to control said switches in response to said configuration data from said compiler means.

8. The adaptive processing systems as described in claim 3, wherein said memory means are also coupled to said configuration control means.

9. The adaptive processing system as described in claim 3, further including pre-processing means connected to said memory means for receiving said input signals and transferring signals to said memory means for storage.

10. The adaptive processing system as described in claim 3, further including post-processing means connected to said memory means for receiving a processed input signal and for generating an output signal from said signal.

11. The adaptive processing system as described in claim 3, further including array processing means connected to said memory means and controlled by said configuration means for generating filter coefficients for use by said processing elements.

12. The adaptive processing system as described in claim 2, wherein each of said processing elements includes means to perform arithmetic functions, through which selected of said terminals are coupled by operating said switches.

13. The adaptive processing system as described in claim 2, wherein each of said processing elements includes:

multiplying means having a first input connected to a first switch, a second input and an output;

storage means having an input connected to a second switch and an output connected to said second input of said multiplying means;

adder means having a first input connected to said output of said multiplying means, a second input connected to said second switch, and an output connected to a third switch; and

delay means having an input connected to said first switch, a control terminal for receiving configuration data for setting an amount of delay of said delay means, and an output.

14. An adaptive processing system for real-time signal processing of one or more input signals in parallel-pipeline fashion, comprising:

an array of a plurality of individually addressable and configurable processing elements for receiving and processing said input signals, each processing element having a plurality of programmable switches and wherein selected programmable switches of adjacent processing elements are slave to each other, said processing elements contiguously arranged for data flow between elements for linear and non-linear operations;

interface means for inputting instructions defining the processing configuration of the individually configurable processing elements;

configuration control means coupled to said processing elements and said interface means and responsive to said interface means for generating configuration data defining the configuration of each element switch of said array to control data flow within and between contiguous processing elements thereof to enable processing of said input signal(s) by said processing elements according to the input instructions; and

memory elements connected between said control means and said processing elements.

15. The adaptive processing system as described in claim 14 further including pre-processing means connected to said memory elements for receiving said input signal(s) and transferring said input signal(s) to said memory elements for storage.

16. The adaptive processing system as described in claim 14 further including post-processing means connected to said memory elements for receiving a processed input signal and for generating on output signal from said system.

17. The adaptive processing system as described in claim 14 further including array processing means connected to said memory elements and controlled by said configuration control means for generating filter coefficients for use by said processing elements.

18. The adaptive processing system as described in claim 14 further including signal database means connected to said interface means and said configuration control means for storing a set of all signal parameters which may be processed by said system.

19. The adaptive processing system as described in claim 14 wherein each of said processing elements includes:

multiplying means having a first input connected to a first programmable switch, a second input and an output;

storage means having an input connected to a second programmable switch and an output connected to said second input of said multiplying means;

adder means having a first input connected to said output of said multiplying means, a second input connected to said second programmable switch, and an output connected to a third programmable switch; and

delay means having an input connected to said first programmable switch, a control terminal for receiving configuration data for setting an amount of delay of said delay means, and an output.

20. An adaptive processing system for real-time signal processing of one or more input signals in parallel-pipeline fashion, comprising:

a random access processor having an array of processing elements individually addressable and internally configurable for receiving and performing the parallel-pipeline processing of the one or more input signals;

a man-machine interface for inputting instructions defining the processing configuration of the individually configurable processing elements;

a signal data base connected to the man-machine interface for storing a set of all signal parameters processable by the system;

a compiler coupled to the signal data base and responsive to the instructions from the man-machine interface for interpreting the instructions in terms of the signal parameters stored in the signal database and, in response thereto, for generating configuration signals for the array necessary to estimate unknown or unspecified signal parameters in the one or more input signals;

a central processing unit responsive to the configuration signals from said compiler for generating configuration data defining the internal configuration of the elements of said array and coupling the configuration data to the random access processor for controlling data for flow within and between contiguous processing elements thereof to enable processing of the one or more input signals by the random access processor according to the input instructions;

a multi-port random access memory (RAM) connected to the random access processor for providing storage for the central processing unit and a signal path bus for the one or more input signals to and from the random access processor; and

a first parallel interface circuit connected to said multi-port RAM for receiving said one or more input signals and for providing pre-processing of said input signals.

21. The adaptive processing system as described in claim 20, wherein said random access processor includes at least first and second contiguous processing elements, each having first, second and third programmable switches, said programmable switches having operational states controlled by said configuration data.

22. The adaptive processing system as described in claim 21 wherein said first programmable switch of said second processing element is normally slaved to said third programmable switch of said first processing element

23. The adaptive processing system as described in claim 21 wherein each of said processing elements includes:

a multiplier having a first input connected to said first programmable switch, a second input and an output;

a latch having an input connected to said second programmable switch and an output connected to said second input of said multiplier;

an adder having first input connected to said output of said multiplier, a second input connected to said second programmable switch, and an output connected to said third programmable switch; and

a programmable delay element having an input connected to said first programmable switch, a control terminal for receiving configuration data for setting an amount of delay of said programmable delay element and an output.

24. The adaptive processing system as described in claim 20 further including a second parallel interface circuit connected to said multiport RAM for receiving said one or more input signals following processing thereof by said random access processor.

25. A random access processor for processing signals at high data rates comprising a systolic array of contiguously arranged processing elements, the processing elements coupled such that signals are clocked from one processing element into an adjacent processing element in a parallel-pipeline fashion, each processing element including programmable means for dynamically configuring a coupling of a signal input of the processing element, a signal output of the processing element, means for adding and means for multiplying, the configuration determining a processing function carried out by the processing element.

26. The random access processor for processing signals according to claim 25 wherein each processing element is further comprised of means for delaying a signal received by the processing element, and wherein the programmable means for selectively configuring a coupling couples the signal input, signal output, means for adding, means for multiplying and means for delaying.

27. The random access processor according to claim 26 wherein the means for configuring the coupling in each processing element of the systolic array is comprised of a plurality of programmable switches, each programmable switch having a plurality of predetermined states, the states determining the configuration of the processing element.

28. The random access processor according to claim 27 wherein the means for delay is programmable with a predetermined period of delay.

29. The random access processor according to claim 28 wherein the means for multiplying is programmable with a predetermined coefficient of multiplication.

30. The random access processor according to claim 25 wherein each processing element comprising the systolic array is coupled to an adjacent processing element in the array by a plurality of ports for receiving processed signals from the adjacent processing element, each port being coupled to the means for dynamically configuring the coupling of the signal input, the signal output, the means for adding and the means for multiplying.

31. A means for dynamically configuring a systolic array of processing elements for real-time digital signal processing of input signals with linear and nonlinear operation, comprising:

means for individually configuring a processing structure of each processing element in a systolic array of processing elements, the processing elements coupled for parallel-pipeline processing of digital signals with linear and non-linear operations, where a configuration of the structure of each of the processing element in the systolic array determines the operation performed by the systolic array;

memory means for transmitting to each processing element in the systolic array an input signal and for receiving from each processing element an output signal.

32. The means for dynamically configuring a systolic array according to claim 31 further comprising an array processor means for dynamically generating a coefficient of multiplication for each processing element, the means for dynamically generating coupled to the memory means.

33. The means for dynamically configuring a systolic array according to claim 32 further comprising:

a compiler for compiling a program from signal processing instructions;

signal data base means for storing a set of all signal parameters, the signal data base means coupled to the compiler; and

a central processing unit for executing the program and generating configuration data with which to configure each of the processing units, the central processing unit coupled to the memory means.