Synthetic netlist system and method

• US 4,967,367 A
• Filed: 11/21/1988
• Issued: 10/30/1990
• Est. Priority Date: 11/21/1988
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Piednoir, Jacques-Oliver
• Primary Examiner(s): Chin, Gary
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US07/273,479
• Time in Patent Office: 708 Days
• Field of Search: 364/489, 364/491, 364/300, 364/200, 364/900, 364/578, 364/490, 324/73 R, 324/73 AT
• US Class Current: 716/102
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A system and method is disclosed for generating a synthetic netlist which mimics the size and complexity of a specified target circuit. The first step of synthetic netlist generation is to generate an abstract of the netlist of a known circuit of the same type as the specified target circuit. Information in the abstract specifies the relative usage rates of the circuit elements in the known circuit and the complexity of the interconnections between circuit elements and circuit signals. The second step is to generate a synthetic netlist, scaled to include a specified number of circuit elements. The circuit elements in the synthetic netlist are interconnected in a sequential process so as to have the interconnection complexity specified by the abstract of the known circuit. While the circuit represented by the resulting synthetic netlist would not perform any useful circuit function, the layout of the synthetic netlist will accurately represent the size and interconnection complexity of the specified target circuit. The synthetic netlist generated by the present invention is suitable for use with a silicon complier so as to generate a circuit layout representative of the specified target circuit.

Claims

1. A synthetic netlist generator, comprising:

abstract means for receiving a specified netlist representing a known circuit, said specified netlist including a representation of the interconnections between a specified set of circuit elements in said known circuit, and for generating an abstract representing the circuit elements used, the distribution of circuit elements and the complexity of the interconnections between said circuit elements in said known circuit; and

netlist means for receiving said abstract and generating a new, synthetic circuit netlist, said synthetic circuit netlist representing a set of selected circuit elements with selected interconnections therebetween, said set having a specified number of circuit elements, wherein the circuit elements used, the distribution of said selected circuit elements and the complexity of the selected interconnections therebetween are in accordance with said abstract.

2. The synthetic netlist generator of claim 1, said known circuit having circuit elements distributed over a plurality of logic levels, said abstract means including means for generating an abstract representing the number of logic levels in said known circuit and the distribution of circuit elements among said logic levels, said abstract means further including means for determining the number of circuit neighbors for each circuit element in said known circuit and for including in said abstract a representation of the distribution of the number of circuit neighbors for the circuit elements in said known circuit.

3. The synthetic netlist generator of claim 2, said netlist means including means for generating a list having a specified number of circuit elements, the distribution of said selected circuit elements being in accordance with said abstract, and for then generating representations of interconnections of said circuit elements in said list, said interconnections being selected so that said synthetic circuit netlist represents a circuit having the same number of logic levels s said known circuit and so that the distribution of circuit elements among said logic levels and the distribution of the number of circuit neighbors for the circuit element in said synthetic circuit netlist are in accordance with said abstract.

4. The synthetic netlist generator of claim 3, said interconnections in said known circuit comprising signals, each said signals having an associated fanout,

said abstract means including means for determining the fanout of each said signal in said known circuit and for including in said abstract a representation of the distribution of fanout values for the signals in said known circuit;

said netlist means including means for generating representations of signals interconnecting said circuit elements in said list, said signal interconnections being selected so that the distribution of fanout values among said signals is in accordance with said representation of the distillation of fanout values in said abstract.

5. A method of generating a synthetic netlist, comprising the steps of:

receiving a specified netlist representing a known circuit, said specified netlist including a representation of the signal interconnections between a specified set of circuit elements in said known circuit, said known circuit having circuit elements distributed over a plurality of logic levels;

generating an abstract representing the circuit elements used, the distribution of circuit elements, the complexity of the interconnections between said circuit elements in said known circuit, and the number of logic levels in said known circuit;

generating a new, synthetic netlist having a specified number of circuit elements, the circuit elements used and the distribution of said circuit elements being in accordance with said abstract; and

generating signal interconnections of said circuit elements in said synthetic netlist so as to represent a circuit having the number of logic levels specified in said abstract, and selecting said signal interconnections so that the complexity of the selected interconnections between said circuit elements are in accordance with said abstract.

6. The method of claim 5, said step of generating an abstract further including the steps of determining the number of circuit neighbors for each circuit element in said known circuit and generating a representation in said abstract of the distribution of the number of circuit neighbors for the circuit elements in said known circuit;

said netlist generating step including the step of selecting said signal interconnections so that the distribution of the number of circuit neighbors for the circuit elements in said synthetic netlist is in accordance with said abstract.

7. The method of claim 6, said signal interconnections in said known circuit comprising signals, each having an associated fanout;

said step of generating an abstract further including the steps of determining the fanout of each said signal in said known circuit and for including in said abstract a representation of the distribution of fanout values for the signals in said known circuit;

said signal interconnection generating step including the step of selecting said signal interconnections so that the distribution of fanout values among said signal interconnections in said synthetic netlist is in accordance with said representation of the distribution of fanout values in said abstract.

8. A method of generating a synthetic netlist, comprising the steps of:

receiving a specified netlist representing a known circuit having a multiplicity of circuit elements, said specified netlist further representing signals interconnecting said circuit elements;

said known circuit having circuit elements distributed over a plurality of logic levels;

generating an abstract representing the circuit elements used, the distribution of circuit elements, the complexity of the interconnections between said circuit elements in said known circuit, the number of logic levels in said known circuit, and the distribution of said circuit elements among said logic levels;

generating a synthetic netlist having a specified number of circuit elements, the circuit elements used, the distribution of said circuit elements being in accordance with said abstract; and

generating signal interconnections of said circuit elements in said synthetic netlist so as to represent a circuit having the number of logic levels specified in said abstract, and selecting said signal interconnections so that the complexity of the selected interconnections between said circuit elements and the distribution of circuit elements among said logic levels are in accordance with said abstract.