Bus driving and decoding circuit

• US 4,967,390 A
• Filed: 08/10/1988
• Issued: 10/30/1990
• Est. Priority Date: 09/16/1987
• Status: Expired due to Fees

• Current Assignee: Varian Semiconductor Equipment Associates Incorporated (Applied Materials Incorporated)
• Original Assignee: Bull H.n. Information Systems Italia SpA
• Inventors: Rendina, Francesco, Savogin, Lucio
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/230,636
• Time in Patent Office: 811 Days
• Field of Search: 364/900 MS File
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

Bus driving and decoding circuit for validating the decoding of signals put on the bus by said drivers, comprising a plurality of driver elements and a decoder connected to the bus, the drivers being grouped in at least two sets, each implemented in one integrated component having a control input for enabling the opening of the related driver set, the control input receiving an enabling signal which is further input to one driver in each integrated component, so as to obtain at the output of the one driver a validation signal (V1, V2) for the decoder, each validation signal having an intrinsic delay equal to the propagation delay of the related integrated component, the circuit comprising further a delay element, located upstream or downstream of driver elements which generate the validation signals, to provide each of the validation signals with an incremental delay sufficing to cover the propagation delay spread specific to the related integrated component, the decoder being enabled by the joint assertion of the validation signals.

Claims

1. A bus driving and decoding circuit for putting on a bus of a data processing system a set of binary signals and for decoding said set of signals put on said bus, at least one said set of signals including validated signal which has a minimum propagation delay, comprising a plurality of driver elements coupled to said bus, each said driver element having a signal output coupled to said bus for inputting one of said binary signals on said bus, and a decoder coupled to said bus and having inputs connected to said bus for receiving said set of signals, said plurality of drivers comprising at least two sets, each set being implemented in a single integrated component, each integrated component having a control input for enabling the transfer at the output of the drivers in said set of signals input to said driver set, with a propagation delay intrinsically equal in all drivers of said driver set and a minimum spread from driver to driver of said driver set, characterized in that said circuit comprises:

first means for jointly applying an enabling signal (ABI) to said control input of said integrated components and to the input of a first driver in each set, to obtain as output from said first driver in each set a validation signal (V1,V2) which is input to said decoder, said validation signal having a delay intrinsically equal to the propagation delay of the related set, and

delay means upstream or downstream from said first driver of each set to provide each of said validation signals to said decoder with an incremental delay sufficing to overlap the propagation delay spread of the related driver set, said decoder being enabled by the joint assertion of said validation signals.

2. A bus driving and decoding circuit as claimed in claim 1, wherein said delay means is located downstream of said first driver of each set and consists of a logic gate (OR,AND,NOR,NAND).

3. A bus driving and decoding circuit as claimed in claim 1, wherein a second driver of at least one of said driver sets receives as input a further enabling signal (AS1) to obtain at the output of said second driver a further validation signal (AS) for said decoder, the transition of said further enabling signal (AS1) from asserted to deasserted causing the subsequent and delayed removal of said enabling signal (ABI) so that said further validation signal (AS) is deasserted and inhibits said decoder before said drivers are disabled.

4. A bus driving and decoding circuit as claimed in claim 3 wherein said further enabling signal (AS1) is input to a second driver of each of said driver sets, to obtain at the output of said second driver of each set a validation signal (AS, ASA) for said decoder.