Method of fabricating back diffused bonded oxide substrates

• US 4,968,628 A
• Filed: 12/09/1988
• Issued: 11/06/1990
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Gaul, Stephen J., Rouse, George V., McLachlan, Craig J., Delgado, Jose A.
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US07/282,064
• Time in Patent Office: 697 Days
• Field of Search: 437/21, 437/62, 437/924, 437/974, 437/67, 148/DIG. 85, 148/DIG. 12, 148/DIG. 141
• US Class Current: 438/406
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 438/928 Front and rear surface processing

Abstract

A method including forming an alignment moat of a first depth on a first surface of a substrate and performing all backside processing, forming a first oxide layer on the first surface and oxide bonding it to a handling wafer by oxide bonding. The substrate is then thinned from a second surface opposite the first surface down to a thickness less than the depth of the alignment moat so the alignment moat is exposed at a third surface for front side processing.

Claims

1. A method of fabricating back diffused, oxide bonded substrates comprising:

forming an alignment moat of a first depth in a first surface of a substrate having a first conductivity type;

introducing impurities of a second conductivity type through said first surface to form second regions using said alignment moat for alignment;

introducing impurities of said first conductivity type through said first surface to form first regions using said alignment moat for alignment;

positioning a handle wafer having a first oxide layer thereon on said first surface and heating to bond said substrate to said handle wafer;

removing portions of said substrate from a second surface opposite said first surface until said substrate has a thickness less than said first depth to expose said alignment moat at a third surface; and

subsequently performing process steps on said third surface using said alignment moat for alignment.

2. A method according to claim 1, wherein forming said alignment moat includes masking said first surface and etching exposed portions of said first surface.

3. A method according to claim 2, wherein said etching includes chemical anisotropic etching.

4. A method according to claim 1, wherein forming said alignment moat includes forming an alignment moat of said first depth in the range of 5 to 30 microns.

5. A method according to claim 1, wherein removing portions of said substrate includes grinding and etching.

6. A method according to claim 1, wherein introducing said second conductivity type impurities includes diffusing said second conductivity type impurities to form second regions of a depth of at least equal to said first depth.

7. A method according to claim 6, wherein said first depth is in the range of 10 to 40 microns.

8. A method according to claim 6, wherein said first conductivity type impurities forms first regions of a depth substantially less than said first depth.

9. A method according to claim 1, wherein:

prior to said introduction of said first conductivity type impurities, forming a second oxide layer on said first surface and forming an oxide free mask on said second oxide layer;

introducing said first conductivity type impurities through openings in said mask;

removing said mask; and

positioning said first oxide layer on said second oxide layer and heating to bond.

10. A method according to claim 1, wherein introducing said first conductivity type impurities includes:

forming a mask of oxide on said first surface,

introducing said first conductivity type impurities through openings in said mask,

removing said mask to expose said first surface, and

forming a second layer of oxide on said first surface, and said positioning includes;

positioning said first oxide layer on said second oxide layer and heating to bond.

11. A method according to claim 1, wherein said processing steps performed on said third surface includes forming isolation trenches extending from said third surface through said substrate to said first oxide layer at said first surface to form dielectrically isolated islands.

12. A method according to claim 11, wherein forming said isolation trenches includes forming a mask and reactive ion etching through openings in said mask.

13. A method according to claim 12, including filling said isolation trenches with an insulator and planarizing.

14. A method according to claim 11, wherein said process steps performed on said third surface include introducing impurities into said substrate and said second regions.

15. A method according to claim 1, wherein said process steps performed on said third surface include introducing impurities into said substrate and said second regions.

16. A method according to claim 1, wherein said alignment moat has a void at said first surface at said positioning step.

17. A method according to claim 1 wherein forming said alignment moat includes chemical anisotropic etching;

and

wherein said processing steps performed on said third surface includes forming isolation trenches extending from said third surface through said substrate to said first oxide layer at said first surface to form dielectrically isolated islands.

18. A method according to claim 17 wherein forming said isolation trenches includes forming a mask and reactive ion etching through openings in said mask, said alignment moat being within one of said mask openings.

19. A method according to claim 18 including filling said isolation trenches with an insulator and planarizing.