Programmable speed/power arrangement for integrated devices having logic matrices
First Claim
1. A programmable speed/power arrangement for an integrated device having a logic matrix comprising:
- (a) switching means for switching the logic matrix between a low power, stand-by mode and a high power, high speed operation mode;
(b) switch operating means responsive to at least one of a wake-up pulse generated externally of the logic of the matrix and a wake-up pulse generated internally of the logic matrix for operating the switching means; and
(c) internal wake-up pulse generator means, connected to the switch operating means, for selectively generating an internal wake-up pulse in dependence upon processing requirements.
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Abstract
A programmable speed/logic arrangement for integrated devices having logic matrices which permits a user to determine the method by which the a logic matrix of an integrated circuit is switched between a low power standby and a high power operation mode. The arrangement includes a switching circuit for switching the logic matrix between modes, switch operating circuit responsive to at least one of internal and external wake-up pulses for operating the switching circuit, and an internal pulse generator for selectively generating a wake-up pulse internally of the matrix. The logic matrix is provided with a specific addressable location which is responsive to an appropriate address to generate the internal wake-up pulse as well as a dedicated input responsive to an externally generated wake-up pulse. Further, high/low power fuses or E/EE CMOS devices can be employed to programmably connect the logic matrix to different levels of high power sources. The plural power sources may be a plurality of parallel switches for each column.
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Citations
16 Claims
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1. A programmable speed/power arrangement for an integrated device having a logic matrix comprising:
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(a) switching means for switching the logic matrix between a low power, stand-by mode and a high power, high speed operation mode; (b) switch operating means responsive to at least one of a wake-up pulse generated externally of the logic of the matrix and a wake-up pulse generated internally of the logic matrix for operating the switching means; and (c) internal wake-up pulse generator means, connected to the switch operating means, for selectively generating an internal wake-up pulse in dependence upon processing requirements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification