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Programmable speed/power arrangement for integrated devices having logic matrices

  • US 4,968,900 A
  • Filed: 07/31/1989
  • Issued: 11/06/1990
  • Est. Priority Date: 07/31/1989
  • Status: Expired due to Term
First Claim
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1. A programmable speed/power arrangement for an integrated device having a logic matrix comprising:

  • (a) switching means for switching the logic matrix between a low power, stand-by mode and a high power, high speed operation mode;

    (b) switch operating means responsive to at least one of a wake-up pulse generated externally of the logic of the matrix and a wake-up pulse generated internally of the logic matrix for operating the switching means; and

    (c) internal wake-up pulse generator means, connected to the switch operating means, for selectively generating an internal wake-up pulse in dependence upon processing requirements.

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