Gate enhanced rectifier

• US 4,969,028 A
• Filed: 03/08/1990
• Issued: 11/06/1990
• Est. Priority Date: 12/02/1980
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Baliga, Bantval J.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Fahmy, Wael
• Application Number:
  US07/492,377
• Time in Patent Office: 243 Days
• Field of Search: 357/23.3, 357/23.4, 357/23.8, 357/38, 357/43
• US Class Current: 257/124
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0852 of DMOS transistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

A high power semiconductor rectifier is constructed so that the rectifier is normally off and can be switched on by applying a bias signal to a gate of a metal-insulator-semiconductor structure monolithically integrated with the rectifier in such a manner as to induce a conducting channel between the anode and cathode of the rectifier. The device has both forward and reverse blocking capability and a low forward voltage drop when in the conducting state. The device has a very high turn-off gain and both high dV/dt and di/dt capabilities.

Claims

1. A gate controlled semiconductor power device for controlling the flow of power to a load comprising:

a body of semiconductor material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity disposed contiguous to and forming a pn-junction with said carrier injection region, and a first island of said one type conductivity disposed within said base region and spaced from said carrier injection region, said first island and said base region both extending to a first surface of said body of semiconductor material;

a first power electrode disposed in ohmic contact with said carrier injection region;

a second power electrode disposed in ohmic contact with said first island and contacting said body only in regions of said one type conductivity; and

an insulated gate electrode disposed on said first surface adjacent to but electrically insulated from said second power electrode and overlying a portion of said first island which extends from said second power electrode to said base region to control conduction of opposite type conductivity carriers in a channel within said first island extending from said second power electrode to said base region;

said insulated gate electrode in response to an appropriate gate bias inducing said channel with opposite type conductivity in said first island for conductivity coupling opposite type conductivity carriers from said second power electrode to said opposite type conductivity base region to render said device conductive between said first and second power electrodes and in response to reversal or removal of said gate bias repressing said channel for decoupling said second power electrode and said base region to render said device nonconductive between said first and second power electrodes.

2. The semiconductor power device of claim 1 wherein said second power electrode is disposed directly adjacent said insulated gate electrode and contacts only said first island of said body.

3. The semiconductor power device of claim 1 wherein said base region and said second power electrode are each constructed and arranged to be conductively contiguous with said channel region.

4. The semiconductor power device of claim 1 wherein said body further includes a second island disposed within said base region outside said first island, said second island extending to said first surface adjacent said insulated gate electrode and being of said opposite type conductivity and more heavily doped than the portion of said base region adjacent thereto.

5. The semiconductor device of claim 1 wherein said carrier injection region and said first island comprise semiconductor material of P-type conductivity and said base region comprises semiconductive material of N-conductivity type.

15. The semiconductor device of claim 1 wherein:

said carrier injection region extends to a second surface of said body of semiconductor material, said second surface being opposed to said first surface; and

said first electrode is disposed on said second surface.

16. The semiconductor device of claim 15 wherein:

said base region spaces said carrier injection region from said first surface.

17. The semiconductor device of claim 16 wherein:

said second electrode is disposed on said first surface.

18. The semiconductor device of claim 4 wherein said base region spaces said second island from said first island and said charge injection region.

23. The semiconductor power device of claim 1 wherein said device is capable of carrying an average current density of at least 50 amps/cm².

6. A gate controlled semiconductor device comprising:

a body of semiconductor material and an electrode system;

said body of semiconductor material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity adjoining said carrier injection region and forming a pn junction therewith, and a first island of said one type conductivity disposed within said base region, forming a pn junction therewith and spaced from said carrier injection region by said base region, said first island extending to a first surface of said body;

said electrode system consisting of a first electrode, a second electrode, and an insulated gate electrode, said first electrode disposed in ohmic contact with said carrier injection region, said second electrode disposed in ohmic contact with said first island of said body and said insulated gate electrode disposed adjacent to and insulated from said first island and said second electrode;

said insulated gate electrode comprising a conductor layer with an insulation layer disposed between it and said body and said second electrode and in response to an appropriate bias, inducing a channel of said opposite type conductivity in said first island beneath said insulated gate electrode, said channel conductivity coupling opposite conductivity type carriers from said base region to said second electrode for facilitating opposite type carrier current flow in said body between said first and second electrodes during gate enabled conduction.

7. The semiconductor device of claim 6 wherein said base region and said second electrode are each constructed and arranged to be conductively contiguous with said channel.

8. The semiconductor device of claim 6 wherein said body further includes a second island disposed in said base region outside said first island, said second island extending to said first surface adjacent said insulated gate electrode and being of said opposite type conductivity and more heavily doped than the portion of said base region adjacent thereto.

9. The semiconductor device of claim 6 wherein said base region extends to said first surface and said insulated gate electrode extends along said first surface adjacent to a portion of said base region, said insulated gate electrode and said base region being so constructed and arranged that upon suitable biasing of said insulated gate electrode an accumulation layer of said opposite type conductivity carriers is induced in said base region beneath said insulated gate electrode.

10. The semiconductor device, of claim 6 wherein said carrier injection region and said first island comprise semiconductor material of P-type conductivity and said base region comprises semiconductor material of N-type conductivity.

11. The semiconductor device of claim 6 wherein said second electrode forms an ohmic contact with said body only in areas of said one type conductivity and is directly adjacent to, but electrically insulated from, said insulated gate electrode.

19. The semiconductor device of claim 6 wherein:

said carrier injection region extends to a second surface of said body of semiconductor material, said second surface being opposed to said first surface; and

said first electrode is disposed on said second surface.

20. The semiconductor device of claim 19 wherein:

said base region spaces said carrier injection region from said first surface.

21. The semiconductor device of claim 20 wherein:

said second electrode is disposed on said first surface.

22. The semiconductor device of claim 8 wherein said base region spaces said second island from said first island and said charge injection region.

24. The semiconductor device of claim 6 wherein said device is capable of carrying a current density of at least 50 amp/cm².

12. A gate controlled semiconductor device comprising:

a body of semiconductor material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity contiguous to and forming a pn junction with said carrier injection region, and a first island of said one type conductivity disposed within said base region and spaced from said carrier injection region;

a first electrode disposed in ohmic contact with said carrier injection region;

a second electrode disposed in ohmic contact with said body only in regions of said one type conductivity and being in ohmic contact with said first island;

said first island and said base region forming a first junction blocking conduction in a first polarity between said first and second electrodes;

said carrier injection region and said base region forming a second junction blocking conduction in an opposite polarity between said first and second power electrodes; and

a gate electrode disposed adjacent to and insulated from said first island between said first junction and said second electrode, said gate electrode establishing, in response to an appropriate gate bias, an opposite type conductivity conductive link for controllably coupling said base region to said second electrode to shunt said second junction and render the device conductive to main bias potentials applied across the first and second electrodes in said first polarity, said gate electrode in response to reversal or removal of said gate bias potential repressing said opposite type conductivity conductive link for controllably decoupling said first and second electrodes to render said device nonconductive to main bias potentials of said first polarity.

13. The semiconductor device of claim 12 wherein:

said body of semiconductor material has first and second opposed major surfaces;

said base region and said first island both extend to said first major surface; and

said carrier injection region extends to said second major surface.

14. The semiconductor device of claim 12 wherein:

said base region spaces said carrier injection region from said first major surface.

25. The semiconductor device of claim 12 wherein said device is capable of carrying a current density of at least 50 amps/cm².

26. A gate controlled semiconductor device comprising:

a body of semiconductors material including a carrier injection region of one type conductivity, a base region of the opposite type conductivity disposed contiguous to and forming a pn-junction with said carrier injection region, and a first island of said one type conductivity disposed within said base region and spaced from said carrier injection region, said first island and said base region both extending to a first surface of said body of semiconductor material;

a first electrode disposed in ohmic contact with said carrier injection region;

a second electrode disposed in ohmic contact with said first island and contacting said body only in regions of said one type conductivity; and

an insulated gate electrode disposed on said first surface adjacent to, but electrically insulated from, said second electrode and overlying a portion of said first island which extends from said second electrode to said base region to control conduction of opposite type conductivity carriers in a channel within said first island extending from said second electrode to said base region;

said insulated gate electrode in response to an appropriate gate bias including said channel with opposite type conductivity in said first island for conductivity coupling opposite type conductivity carriers from said second power electrode to said opposite type conductivity base region to render said device conductive between said first and second electrodes and in response to reversal or removal of said gate bias repressing said channel for decoupling said second electrode and said base region to render said device nonconductive between said first and second electrodes.

27. The semiconductor device of claim 26 wherein said second electrode is disposed directly adjacent said insulated gate electrode and contacts only said first island of said body.

28. The semiconductor device of claim 26 wherein said base region and said second electrode are each constructed and arranged to be conductively contiguous with said channel region.

29. The semiconductor device of claim 26 wherein said body further includes a second island disposed within said base region outside said first island, said second island extending to said first surface adjacent said insulated gate electrode and being of said opposite type conductivity and more heavily doped than the portion of said base region adjacent thereto.

30. The semiconductor device of claim 26 wherein said device is capable of carrying an average current density of at least 50 amps/cm².