Method of generating discretization grid for finite-difference simulation

• US 4,969,116 A
• Filed: 09/28/1988
• Issued: 11/06/1990
• Est. Priority Date: 09/29/1987
• Status: Expired due to Term

• Current Assignee: Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Wada, Tetsunori, Oosawa, Shinji
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/251,165
• Time in Patent Office: 769 Days
• Field of Search: 364/578, 364/488-491
• US Class Current: 703/13
• CPC Class Codes: G06F 30/23 using finite element methods [FEM] or finite difference methods [FDM]

Abstract

A method of generating a discretization grid for a finite-difference simulation capable of simulating an object with a complex cross-sectional configuration accurately is disclosed. The method includes the step of generating grid through each vertex of the polygonal figure representing the cross-sectional configuration, and the step of generating additional grid through each intersection of the grid and the segments of the polygonal figure not parallel to the grid.

Claims

1. A method of evaluating the characteristics of a semiconductor device, comprising the steps of:

(a) representing a cross section of the semiconductor device by a polygonal figure;

(b) generating rectangular grids to locate one grid intersection point over each vertex of the polygonal figure;

(c) generating additional rectangular grids in order to locate one grid point over each intersection of rectangular grids generated at step (b) and segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at step (b); and

(d) evaluating the characteristics of the semiconductor device on the grid points of the rectangular grids generated at steps (b) and (c).

2. The method of claim 1, further comprising the step of:

(e) generating additional rectangular grids to locate one grid point over each intersection of the rectangular grids generated at step (c) and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at the step (c), as well as to locate one grid point over each intersection of the rectangular grids generated at this step and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at this step;

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (c).

3. The method of claim 2, further comprising the step of:

(f) generating additional rectangular grids in a vicinity of boundaries between different materials contained in the semiconductor device;

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at the step (f).

4. The method of claim 3, further comprising the steps of:

(g) generating additional rectangular grids to locate one grid point over each intersection of the rectangular grids generated at step (f) and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at step (f);

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (g).

5. The claim of claim 4, further comprising the step of:

(h) generating additional rectangular grids to locate one grid point over each intersection of the rectangular grids generated at step (g) and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at step (g), as well as to locate one grid point over each intersection of the rectangular grids generated at this step and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at this step; and

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (h).

6. The method of claim 1, further comprising the step of:

(i) generating additional rectangular grids such that each separation between adjacent lines of the rectangular grids generated at steps (b), (c) and this step has a ratio not greater than a prescribed value with respect to an adjacent separation; and

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (i).

7. The method of claim 6, further comprising the step of:

(j) generating additional rectangular grids to locate one grid point over each intersection of the rectangular grids generated at stop (i) and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at step (i);

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (j).

8. The method of claim 7, further comprising the step of:

(k) generating additional rectangular grids to locate one grid point over each intersection of the rectangular grids generating at step (j) and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at step (j), as well as to locate one grid point over each intersection of the rectangular grids generated at this step and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at this step;

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (k).

9. The method of claim 1, further comprising the steps of:

(1) calculating, for each pair of adjacent grid points, a quantity related to the physical properties of the semiconductor device; and

(m) generating additional rectangular grids in regions where the quantity calculated at step (1) varies from one pair of adjacent grid points to an adjacent pair of adjacent grid points by a value greater than a prescribed value;

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (m).

10. The method of claim 9, further comprising the step of:

(n) generating additional rectangular grids to locate one grid point over each intersection of the rectangular grids generated at step (m) and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at step (m);

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (n).

11. The method of claim 10, further comprising the step:

(o) generating additional rectangular grids to locate one grid point over each intersection of the rectangular grids generated at step (n) and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at step (n), as well as to locate one grid point over each intersection of the rectangular grids generated at this step and the segments of the polygonal figure which are not parallel to lines of the rectangular grids generated at this step; and

wherein at step (d) the characteristics of the semiconductor device are also evaluated on the grid points of the rectangular grids generated at step (o).

12. The method of claim 1, wherein at step (d) the grid points are represented by their coordinates with respect to a prescribed coordinated system in evaluating the characteristics of the semiconductor device.

13. The method of claim 12, wherein at step (d) all overlapping coordinates among the coordinates representing the grid points are removed, and all remaining coordinates representing the grid points are rearranged in a prescribed order after all of the overlapping coordinates are removed.

14. The method of claim 3, wherein at step (f) the boundaries between different materials contained in the semiconductor device are determined in accordance with material data containing information of the different materials contained in the semiconductor device.

15. The method of claim 11, wherein at step (i) the additional rectangular grids are generated such that one grid point is located on a mid-point of each separation between adjacent lines of the rectangular grids generated at the steps (b), (c) and (i), which as a ratio greater than a prescribed value with respect to an adjacent separation.

16. The method of claim 13, wherein two of the coordinates representing the grid points are considered overlapping when a distance between these two coordinates is less than a prescribed value.

17. The method of claim 1, wherein at step (d) the characteristics of the semiconductor device are evaluated on a basis of partial differential equations which are discretized by using the grid points of the rectangular grids generated at steps (b) and (c).

18. The method of claim 3, wherein at step (f) the different materials are the semiconductor and conductive materials of the semiconductor device proximate to each other.