Resettable latch circuit

• US 4,970,406 A
• Filed: 06/26/1989
• Issued: 11/13/1990
• Est. Priority Date: 12/30/1987
• Status: Expired due to Fees

• Current Assignee: Gazelle Microcircuits, Inc.
• Original Assignee: Gazelle Microcircuits, Inc.
• Inventors: Pang, Richard F., Fitzpatrick, Mark E., Gouldsberry, Gary R., Chan, Yat-Sum
• Primary Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/372,225
• Time in Patent Office: 505 Days
• Field of Search: 307/291, 307/292, 307/272.1, 307/272.2, 307/279, 307/564, 307/567, 307/272.3
• US Class Current: 327/203
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

A reset circuit incorporated into a latch circuit which comprising a follow portion and a hold portion and generates an output signal at an output terminal in response to an input data signal and a clock signal. A reset signal is applied, via a diode, to the output terminal which causes the output terminal to immediately assume the state of the reset signal without any intervening gate delay.

Claims

1. A reset circuit incorporated into a latch circuit, said latch circuit being of the type which receives a first input data signal and generates a first output signal at a first output terminal, after latching, in response to said first input data signal, said reset circuit operating to set said first output signal at a predetermined high or low state upon application of a first reset signal to said reset circuit, said reset circuit comprising:

a first two terminal nonlinear device with a first terminal coupled to receive said first reset signal and a second terminal coupled to said first output terminal of said latch circuit, whereby, upon application of said first reset signal to said first terminal of said first nonlinear device, said first output terminal will assume the state of said first reset signal prior to said latch circuit latching,

wherein said latch circuit generates a second output signal of a state opposite to that of said first output signal for application to a second output terminal, and wherein a second reset signal of opposite state as said first reset signal is applied to a first terminal of a second two terminal nonlinear device wherein a second terminal is coupled to said second output terminal, so that upon application of said second reset signal to said first terminal of said second nonlinear device, said second output terminal will assume the state of said second reset signal,

wherein said latch circuit incorporates a hold circuit comprising a first differential transistor pair being enabled by an enable signal, said first differential transistor pair comprising a first transistor and a second transistor, said first transistor having a control terminal coupled to said second output terminal and a second terminal coupled to said first output terminal, said second transistor having a control terminal coupled to said first output terminal and a second terminal coupled to said second output terminal, said first transistor and said second transistor having third terminals being coupled together and connected to an enable circuit, said enable circuit, upon application of a first state of said enable signal to said enable circuit, causing a current to be drawn through said first differential pair, and

wherein said second reset signal, through said second nonlinear device, and said second terminal of said second transistor are coupled to said second output terminal via a first level shifting means so that when said second terminal of said second transistor is at a high level, said level shifting means will apply a high signal to said second output terminal, and when said second reset signal is at a low level a low signal will be applied to said second output terminal.

2. The reset circuit of claim 1 wherein said second terminal of said first transistor is coupled to said first output terminal via a second level shifting means.

3. The reset circuit of claim 2 wherein said latch circuit also incorporates a follow circuit comprising a second differential transistor pair, said second differential transistor pair comprising a third transistor and a fourth transistor, said third transistor having a control terminal coupled to receive said first input data signal and a second terminal coupled to said second terminal of said first transistor in said hold circuit, said fourth transistor having a control terminal coupled to receive a second input signal and a second terminal coupled to said second terminal of said second transistor in said hold circuit, said third transistor and said fourth transistor having third terminals being coupled together and connected to said enable circuit, said enable circuit, upon application of a second state of said enable signal to said enable circuit, causing a current to be drawn through said second differential pair, said follow circuit and said hold circuit being alternatively enable by said enable signal.

4. The reset circuit of claim 3 wherein said second input signal is a fixed reference voltage.

5. The reset circuit of claim 3 wherein said second input signal is an inverse of said first input data signal.

6. The reset circuit of claim 3 wherein said enable circuit comprises a fifth and sixth transistor in a third differential transistor pair, wherein said enable signal is applied to a control terminal of said fifth transistor and a second terminal of said fifth transistor is coupled to said third terminals of said third and fourth transistors in said follow circuit, and wherein a reference signal is applied to a control terminal of said sixth transistor and a second terminal of said sixth transistor is coupled to said third terminals of said first and second transistors in said hold circuit, said follow circuit and said hold circuit being alternatively enabled by said enable signal as determined by whether or not the magnitude of said enable signal exceeds the magnitude of said reference signal.

7. The reset circuit of claim 1, 2, 3, 4, 5, or 6 wherein said first and second transistors are bipolar transistors.

8. The reset circuit of claim 1, 2, 3, 4, 5, or 6 wherein said first and second transistors are field-effect transistors.

9. The reset circuit of claim 1, 2, 3, 4, 5, or 6 wherein said first and second transistors are compound semiconductor transistors.

10. The reset circuit of claim 1, 2, 3, 4, 5, or 6 wherein said first and second transistors are gallium arsenide (GaAs) transistors.

11. The reset circuit of claim 1, 5, 6, 7, 8, or 9 wherein said first and second transistors are gallium arsenide (GaAs) field-effect transistors.

12. The reset circuit of claim 1, 2, 3, 4, 5, or 6 wherein said first and second transistors are gallium arsenide (GaAs) bipolar transistors.