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Programmable memory state machine for providing variable clocking to a multimode memory

  • US 4,970,418 A
  • Filed: 09/26/1989
  • Issued: 11/13/1990
  • Est. Priority Date: 09/26/1989
  • Status: Expired due to Term
First Claim
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1. A circuit for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse, the circuit comprising means for providing signals indicating a mode of operation for access to a matrix of memory elements, means responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, and means responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate.

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