Programmable memory state machine for providing variable clocking to a multimode memory
First Claim
1. A circuit for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse, the circuit comprising means for providing signals indicating a mode of operation for access to a matrix of memory elements, means responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, and means responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate.
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Accused Products
Abstract
A circuit for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse, the circuit comprising apparatus for providing signals indicating a mode of operation for access to a matrix of memory elements, apparatus responsive to the signals provided by the apparatus for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, and apparatus responsive to the signals provided by the apparatus for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate.
128 Citations
12 Claims
- 1. A circuit for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse, the circuit comprising means for providing signals indicating a mode of operation for access to a matrix of memory elements, means responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, and means responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate.
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3. A circuit as claimed in calim 2 for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse in which the means for comparing a signal indicating a clock period for a mode with actual clock periods comprises a counter for furnishing signals indicating clock periods, a comparator circuit for comparing signals furnished by the counter with signals furnished by the means for selecting from the plurality of signals depending on the mode of operation to provide signals indicating a clock period, and means responsive to the comparator circuit for providing a signal indicating that the clock period is correct.
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11. A circuit for providing control signals of selectable lengths capable of being driven off of either the rising or falling edge of a clock pulse comprising means for providing signals indicating a mode of operation for access to a matrix of memory elements, a first plurality of registers for storing signals indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, a first multiplexor responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals from the first plurality registers indicating a clock period during which a control signal is to commence and the edge of the clock signal at which such signal is to commence, a first comparator for comparing a signal indicating a clock period for a mode with actual clock periods, and first means for comparing a signal indicating a clock edge for a mode with an actual clock edge;
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a second plurality of registers for storing signals indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate, a second multiplexor responsive to the signals provided by the means for providing signals indicating a mode of operation for providing signals from the second registers indicating a clock period during which a control signal is to terminate and the edge of the clock signal at which such signal is to terminate, a second comparator for comparing a signal indicating a clock period for a mode with actual clock periods, and second means for comparing a signal indicating a clock edge for a mode with an actual clock edge. - View Dependent Claims (12)
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Specification