High performance flight recorder

• US 4,970,648 A
• Filed: 06/29/1989
• Issued: 11/13/1990
• Est. Priority Date: 08/12/1987
• Status: Expired due to Fees

• Current Assignee: Fairchild Space and Defense Corporation (Northrop Grumman Corporation)
• Original Assignee: Fairchild Space and Defense Corporation (Northrop Grumman Corporation)
• Inventors: Capots, Larry H.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Melnick, S. A.
• Application Number:
  US07/373,631
• Time in Patent Office: 502 Days
• Field of Search: 360/5, 371/38, 371/21.3, 371/21.2, 364/424.06, 364/550, 364/900
• US Class Current: 701/14
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A recorder for recording and playing back information. The recorder is particularly useful in vehicles such as aircraft and space vehicles. The recorder has no moving parts and has a plurality of power levels. The recorder has the capability of detecting errors in its memory and to avoid using portions of the memory that have errors. The recorder has multiple channels that can be programmed for input or output use. On demand memory assignment capability permits maximum use of the memory array.

Claims

1. A recording device for recording information comprising:

an input/output interface circuit;

a data storage memory connected to said input/output interface circuit for storing data, said data storage memory being partitioned into memory pages of programable size;

a direct memory access circuit for controlling the input and output of data to and from said data storage memory;

address and data lines interconnecting said direct memory access circuit and said data storage memory;

a central processing unit connected to said direct memory access circuit;

a program memory connected to said central processing unit for storing the operational program for the recording device, said program memory having a test data pattern for memory testing of said data storage memory by cycling the test data pattern throughout the memory pages of said data storage memory to determine good memory pages under control of said central processing unit, and

error detection and correction means connected to said direct memory access circuit and to said input/output circuit for detecting and correcting errors, said error detection and correction means comprising means for appending a check code word to said data and for indicating to said input/output interface circuit the error status when data are read from said data storage memory and for correcting errors when they are detected, means for determining memory pages with non-correctable errors, test means for testing said address and data lines interconnecting said direct memory access circuit and said data storage memory and means for using the test data pattern of said program memory to test the function of said error detection and correction coding means.

2. The recording device for recording information of claim 1 wherein said input/output interface circuit comprises means for simultaneously recording and playing back information.

3. The recording device for recording information of claim 2 wherein said data storage memory has multiple channels for information and further comprising means for providing memory capacity to each channel as needed.

4. The recording device for recording information of claim 3 further comprising means connected to said program memory for interpreting remote commands to establish modes of operation.

5. The recording device for recording information of claim 3 further comprising means connected to said program memory for indicating the status of said recording device.