Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells

• US 4,970,686 A
• Filed: 08/21/1989
• Issued: 11/13/1990
• Est. Priority Date: 08/19/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Mochizuki, Thoru, Asano, Masamichi, Iwase, Taira, Naruke, Yasuo
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US07/396,246
• Time in Patent Office: 449 Days
• Field of Search: 365/96, 365/225.7, 365/200, 357/DIG. 51
• US Class Current: 365/96
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.

Claims

1. A semiconductor memory cell comprising:

(a) a read FET (Field Effect Transistor) and a fusing FET that are connected in series between a read data line and a low voltage source; and

(b) a current fuse inserted between a series node of said FETs and a write data line, said fuse being fused to write data to said read FET.

2. The semiconductor memory cell as claimed in claim 1, wherein, when the data is written, predetermined voltage is applied to a control electrode of said fusing FET, and voltage that is higher than the predetermined voltage is applied to the write data line to put said fusing FET in a snap back action to provide a current, which fuses said current fuse.

3. The semiconductor memory cell as claimed in claim 1, wherein the read data line is formed of any one of polycrystalline silicon, diffusion layer, high melting point metal silicide, metallic layer different from a wiring layer forming the write data line, and at least two of them.

4. The semiconductor memory cell as claimed in claim 1, wherein the semiconductor memory cell is used as a spare memory cell to configure redundancy of a semiconductor memory device to substitute for a faulty normal memory cell of the semiconductor memory device.

5. A semiconductor memory cell comprising:

(a) a read FET (Field Effect Transistor), a drain terminal of said read FET being connected to a read data line while a gate terminal of said read FET being connected to a read work line;

(b) a fusing FET, a drain terminal of said fusing FET being connected to a source terminal of said read FET, a gate terminal of said fusing FET being connected to a write work line, and a source terminal of said fusing FET being connected to a low voltage source; and

(c) a current fuse, one end of said current fuse being connected to a node between the source terminal of said read FET and the drain terminal of said fusing FET, while the other end of said current fuse being connected to a write data line to which predetermined voltage is applied when data is written to said read FET.

6. The semiconductor memory cell as claimed in claim 5, wherein, when the data is written to said read FET, the predetermined voltage is applied though the write word line to the gate terminal of said fusing FET while predetermined voltage is applied through the write data line and said current fuse to the drain terminal of said fusing FET so that said fusing FET is put a snap back action to provide a large current that fuses said current fuse to write the data to said read FET.

7. The semiconductor memory cell as claimed in claim 6, wherein the predetermined voltage applied through the write data line is lower than a drain resistive voltage of said fusing FET with its gate voltage at ground voltage and higher than a secondary breakdown voltage with the gate voltage at a power source voltage.

8. The semiconductor memory cell as claimed in claim 6, further comprising:

switching means connected to the write work line and connecting, when data is read, the write word line to the low voltage source in response to a program signal.

9. A semiconductor memory device comprising:

(a) a group of normal memory cells;

(b) a group of spare memory cells to substitute for faulty normal memory cells of said group of normal memory cells, each of the spare memory cells comprising a read FET (Field Effect Transistor) and a fusing FET that are connected in series between a read data line and a low voltage source, and a current fuse inserted between a series node of the FETs and a write data line, the current fuse being fused when data is written to the read FET;

(c) first selection means for selecting a memory cell from which data is to be read, among said group of normal memory cells;

(d) second selection means for selecting a memory cell from which data is to be read, among said group of spare memory cells;

(e) switching means for selectively outputting one of the data read out of the normal memory cell selected by said first selection means and the data read out of the spare memory cell selected by said second selection means;

(f) writing means for writing data to said group of spare memory cells and for controlling said second selection means such that said second selection means selects any one of said spare memory cells that substitutes for faulty one of said normal memory cells according to an address that is for identifying the one faulty normal memory cell.

10. The semiconductor memory cell as claimed in claim 9, wherein said second selection means comprises memory cells that are NORed to each other, each of the NORed memory cells comprising a read FET (Field Effect Transistor) and a fusing FET that are connected in series between a read data line and a low voltage source and a current fuse inserted between a series node of the FETs and a write data line.