Redundancy and testing techniques for IC wafers

• US 4,970,724 A
• Filed: 12/22/1988
• Issued: 11/13/1990
• Est. Priority Date: 12/22/1988
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (AT&T, Inc.)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Yung, Michael W.
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US07/288,743
• Time in Patent Office: 691 Days
• Field of Search: 371/8.1, 371/8.2, 371/9.1, 371/11.2, 371/11.3, 364/200, 364/900
• US Class Current: 714/3
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]

Abstract

An array of processing element nodes are provided on a semiconductor wafer. A mixed redundancy approach is preferably employed wherein two spare core logic circuit modules 52, 58 are available for use at each node. Each spare core logic module can be connected to one of four different nodes. An H-net 94 interconnects adjacent nodes in such manner that faults in the circuit modules can be easily tested and repaired.

Claims

1. An integrated circuit semiconductor wafer comprising:

an array of primary processing elements (PEs), each PE having primary core logic (CR) circuit means for processing data, primary communication logic (CM) circuit means for controlling data transfer between PEs, and primary communication interconnect (CMI) circuit means for carrying the data between PEs;

a plurality of redundant core logic circuit means for each primary core logic circuit means;

means for selectively connecting one of the redundant core logic circuit means to one of a plurality of primary core logic circuit means;

one redundant communication logic circuit means for each primary communication logic circuit means in each PE; and

one redundant communication interconnect circuit means for each primary communication interconnect circuit means for each PE.

2. The wafer of claim 1 which further comprises:

switch means for selectively connecting one redundant core logic circuit means to said primary communication logic circuit means and to said redundant communication logic circuit means; and

another redundant core logic circuit means being directly connected to said redundant communication logic circuit means.

3. An integrated circuit device having an array of nodes, said device comprising:

a plurality of functional circuit modules for each node, each node including a primary core logic circuit module (CR), one primary and one spare communication logic circuit module (CM), as well as one primary and one spare communication interconnect means (CMI) for carrying data between neighboring nodes; and

said device further comprising a plurality of spare core logic circuit modules;

each node being connectable to at least two of said spare core logic circuit modules thereby providing each node with at least two potential spare core logic circuit modules;

each of said spare core logic circuit modules being selectively connectable to four nodes;

whereby a faulty primary core logic module in each node can be replaced with one of two spares, with each spare being connectable to four different nodes.

4. The device of claim 3 which further comprises:

H-net means for connecting together adjacent nodes such that a first pair of CMs in adjacent nodes are connected together along one route, with another pair of CMs being connected together along another route, with the two routes being electrically connected together by a middle bar which can be cut by external apparatus to isolate the two routes during testing to aid in detecting faulty circuits.

5. The device of claim 4 which further comprises:

a data bus pad for the primary CR and a data bus pad for the spare CR in each node, and connection means for connecting the CRs to their respective data pads, the connection means being such that it can be cut to isolate a faulty CR from its data bus pad.

6. A computer comprising:

a plurality of stacked semiconductor wafers, each said wafer having an array of nodes communicating with corresponding nodes on other wafers, selected wafers having nodes which also communicate with other nodes on the same wafer, each node on said selected wafers including;

a primary core logic circuit means for processing data, a primary communication logic circuit means (CM) directly connected to the primary CR for controlling data transfer between nodes;

a spare CM;

a primary communication interconnect (CMI) circuit means for carrying data between nodes;

a spare CMI switch connected to the primary CMI;

a primary data bus directly connected to the primary CR;

a spare data bus; and

said wafer further comprising an array of spare CRs arranged such that each node is connectable to two spare CRs and such that each spare CR is connectable to four nodes.

7. The computer of claim 6 which further comprises switch means for selectively connecting a first spare CR to the primary CM.

8. The computer of claim 7 wherein a second spare CR is directly connected to the spare CM of each node.

9. The computer of claim 8 which further comprises:

switch means for selectively connecting the first spare CR to the spare data bus; and

switch means for selectively connecting the second spare CR to the spare data bus.

10. An integrated circuit semiconductor wafer comprising:

an array of nodes, each node having a primary core logic (CR) circuit means for processing data and a primary communication logic (CM) means for controlling transfer of data between nodes;

said node further including at least one spare CR connected to at least one spare CM; and

H-net means for connecting together adjacent nodes such that a first pair of CMs in adjacent nodes are connected together along one route, with another pair of CMs being connected together along another route, with the two routes being electrically connected together by a middle bar which can be cut by external apparatus to isolate the two routes during testing to aid in detecting faulty circuits.

11. The wafer of claim 10 which further comprises:

a data bus pad for the primary CR and a data bus pad for the spare CR in each node, and connection means for connecting the CRs to their respective data pads, the connection means being such that it can be cut by external apparatus to isolate a faulty CR from its data bus pad.

13. The method of claim 10 which thereafter comprises:

electrically connecting the primary and spare data bus pads together.

12. A method of testing and repairing a semiconductor wafer having an array of nodes thereon, each node including at least one primary core logic (CR) means for processing data which is connected to a primary communication logic (CM) means for transferring data between nodes, a spare CR connected to a spare CM, a primary data bus pad connected to the primary CR and a spare data bus pad connected to the spare CR, said method comprising:

connecting adjacent nodes together in a generally H-shaped configuration wherein one pair of CMs in adjacent nodes are connected together along a first route, with another pair of CMs in adjacent nodes being connected together along a second route, both routes being connected together by a middle bar portion;

testing each CR and disconnecting it from its associated data bus pad if it is faulty;

thereafter, generating test signals at the primary and spare data bus pads at one node and reading the results at the pads of an adjacent node;

cutting the middle bar if improper test signals are received to thereby isolate the first and second routes;

regenerating the test signals over the isolated first and second routes;

disconnecting from adjacent nodes the CRs and CMs in a route where improper test results are received.