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Redundancy and testing techniques for IC wafers

  • US 4,970,724 A
  • Filed: 12/22/1988
  • Issued: 11/13/1990
  • Est. Priority Date: 12/22/1988
  • Status: Expired due to Term
First Claim
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1. An integrated circuit semiconductor wafer comprising:

  • an array of primary processing elements (PEs), each PE having primary core logic (CR) circuit means for processing data, primary communication logic (CM) circuit means for controlling data transfer between PEs, and primary communication interconnect (CMI) circuit means for carrying the data between PEs;

    a plurality of redundant core logic circuit means for each primary core logic circuit means;

    means for selectively connecting one of the redundant core logic circuit means to one of a plurality of primary core logic circuit means;

    one redundant communication logic circuit means for each primary communication logic circuit means in each PE; and

    one redundant communication interconnect circuit means for each primary communication interconnect circuit means for each PE.

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