Memory management for microprocessor system

• US 4,972,338 A
• Filed: 04/19/1988
• Issued: 11/20/1990
• Est. Priority Date: 06/13/1985
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Crawford, John H., Ries, Paul S.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kulik, Paul
• Application Number:
  US07/185,325
• Time in Patent Office: 945 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism

Abstract

Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level. eyboard

Claims

1. A microprocessor device comprising:

(a) address register means for providing virtual memory addresses;

(b) a bus interface unit providing an interface to address terminals and data terminals of said device;

(c) an address translation unit receiving said virtual memory addresses from said address register means, the address translation unit including;

(i) a segmentation unit having at least one segment descriptor registor storing a segment base address and a limit;

a comparator in said segmentation unit comparing said virtual address to said limit and generating a fault if said limit is exceeded, said limit being of variable size;

the segmentation unit adding said segment base address to said virtual address to produce a linear address having a page information field and an offset;

(ii) a page cache for storing a plurality of page entries and tags for said page entries, said page entries representing memory addresses for pages of fixed size;

means for comparing tags to said page information field of said linear address to produce a match indication, the page cache producing a page entry output corresponding to one of said page entries if the match indication occurs;

(iii) page table addressing means responsive to said match indication and, if the match indication does not indicate a match, generating a page table address from a page base address and at least part of said page information field for transfer to said bus interface unit;

the page table addressing means receiving a page table entry from said but interface unit in response to said page table address, the page table entry corresponding to one of said page entries; and

(d) address generating means connected, in the alternative, to receive either (i) said linear address from said segmentation unit, or (ii) said offset part of said linear address combined with either said page entry output from said page cache or said page table entry from said page table addressing means;

said address generating means producing a physical address for applying to said bus interface unit.

2. A device according to claim 1 combined with a memory external to said device storing said page table entries and accessed by said physical address received from said terminals of said device.

3. A device according to claim 1 wherein said limit has a maximum value equal to an address range addressable by bits in said virtual address.

4. A device according to claim 1 wherein said limit may be larger than or smaller than said fixed page size.

5. A device according to claim 1 wherein said segment descriptor register stores said segment base address, said segment descriptor register further storing attributes of a segment of memory, said attributes including the type of use allowed for locations in said segment of memory and a privilege level for access to said segment of memory.

6. A device according to claim 2 wherin said memory also stores a plurality of segment descriptors for transfer to said segment descriptor register.

7. A device according to claim 1 wherein said page table addressing means generates a first page table address from said page base address and a first part of said page information field, for transfer of the first page table address to said bus interface unit;

and wherein said page table addressing means generates a second page table address from a second page base address received from said bus interface unit and a second part of said page information field, for transfer of said second page table address to said bus interface unit.