TTL-ECL interface circuit

• US 4,973,863 A
• Filed: 12/28/1989
• Issued: 11/27/1990
• Est. Priority Date: 12/28/1989
• Status: Expired due to Fees

• Current Assignee: Eastman Kodak Company
• Original Assignee: Eastman Kodak Company
• Inventors: Gotta, James M. III, Weiner, Frank
• Primary Examiner(s): MILLER JR, STANLEY D
• Application Number:
  US07/458,209
• Time in Patent Office: 334 Days
• Field of Search: 307/455, 307/473, 307/443, 307/456, 307/475, 365/219, 365/189.11, 365/189.12, 365/189.05
• US Class Current: 326/78
• CPC Class Codes: H03K 19/01806 Interface arrangements

Abstract

A circuit for interfacing (parallel format) TTL signals with a serial format ECL signal port includes a parallel-to-serial shift register, a first voltage level shifting stage and an output, TTL-ECL level shifting stage, connected in cascade. Each of the shift register and the first level shifting stage is powered exclusively by an on-board TTL power supply. The output level shifting stage is powered by the on-board TTL supply and from an external connection to a downstream module. The serial output of the shift register is a `positive ECL` signal having a voltage swing corresponding to that of conventional negative polarity ECL signals. From this signal the first level shifting stage produces an intermediate level (quasi analog) signal which transitions between reduced or intermediate high and low voltage levels about a switching leel corresponding to that (e.g. +1.5 volts) of normal TTL signals but having the ELC-type voltage swing. This intermediate level TTL type signal is coupled to the output TTL-ECL voltage level shifting stage to which the signal ECL output port to be coupled to the downstream CRT unit is connected. Since the output stage is readily accessible for connection to an external power supply, specifically a -5 volt ECL supply rail of an adjacent, module, it is powered by both the internal TTL supply bus and by an external jumper connection to the module to which the output ECL signals are to be supplied.

Claims

1. A circuit arrangement for converting first digital signals of a first polarity type which transition between first and second voltage levels, to second digital signals of a second polarity type which transition between third and fourth voltage levels comprising:

a first voltage level shifter which is coupled to receive said first digital signals and produces third signals of said first polarity type, said third signals transitioning between fifth and sixth voltage levels of said first polarity, said fifth and sixth voltage levels being different from said first and second voltage levels and having a differential therebetween corresponding to that between said third and fourth voltage levels;

a second voltage level shifter coupled to receive the third signals produced by said first voltage level shifter, and producing fourth signals which switch, relative to a voltage level corresponding to that at which said first signals switch between said first and second voltage levels, between voltage levels the differential between which corresponds to that between said third and fourth voltage levels; and

a third voltage level shifter coupled to receive said fourth signals and shifting the voltage levels thereof to those of said second digital signals.

2. A circuit arrangement according to claim 1, wherein each of said first and second voltage level shifters is powered exclusively by a first polarity power supply and said third voltage level shifter is powered at each of said first and second polarities.

3. A circuit arrangement according to claim 2, wherein said first polarity is a positive polarity and said second polarity is a negative polarity.

4. A circuit arrangement according to claim 3, wherein said first digital signals are TTL signals and said second signals are ECL signals.

5. A circuit arrangement for interfacing positive polarity TTL signals which transition between first and second voltage levels, to negative polarity ECL signals which transition between third and fourth voltage levels comprising:

a first voltage level shifter which is coupled to receive said TTL signals and produces positive polarity ECL-type signals which transition between fifth and sixth voltage levels of said first polarity, said fifth and sixth voltage levels being different from said first and second voltage levels and having a differential therebetween corresponding to that between said third and fourth voltage levels;

a second voltage level shifter coupled to receive the positive polarity ECL-type third signals produced by said first voltage level shifter, and producing TTL-type signals which switch about a voltage level corresponding to that at which the TTL signals switch between said first and second voltage levels between voltage levels the difference between which corresponds to an ECL signal swing; and

a third, TTL-ECL voltage level shifter, coupled to receive said fourth TTL-type signals and shifting the voltage levels of the binary states thereof to negative polarity ECL levels.

6. A circuit arrangement according to claim 5, wherein each of said first and second voltage level shifters is powered exclusively by a positive polarity TTL power supply and said third TTL-ECL voltage level shifter is powered at each of said positive and negative voltage polarities.

7. A circuit arrangement for converting a parallel input of first digital signals, the binary states of which transition at a first frequency between first and second voltage levels of a first polarity, to a serial output of second digital signals, the binary states of which transition at a second frequency, higher than said first frequency, between third and fourth voltage levels of a second polarity, comprising:

a parallel-to-serial shift register having a parallel input port to which said parallel input of first digital signals is applied, said shift register producing, at a serial output thereof, third digital signals the binary states of which transition at said second frequency between fifth and sixth voltage levels of said first polarity, said fifth and sixth voltage levels being larger than said first and second voltage levels and having a voltage swing corresponding to that between said third and fourth voltage levels;

a first voltage level shifter having an input terminal coupled to receive said third digital signals and producing fourth digital signals of said first polarity and said second frequency, the binary states of said fourth digital signals switching at a voltage level corresponding to that at which said first digital signals switch between the binary states thereof; and

a second voltage level shifter having an input terminal coupled to receive the fourth digital signals produced by said first voltage level shifter and shifting the voltage levels thereof to produce said second digital signals.

8. A circuit arrangement according to claim 7, wherein each of said shift register and said first voltage level shifter is powered by a voltage polarity exclusive of said second polarity.

9. A circuit arrangement according to claim 8, wherein said second voltage level shifter is powered by voltages at each of said first and second polarities.

10. A circuit arrangement according to claim 7, wherein said first digital signals are positive polarity TTL signals and said second digital signals are negative polarity ECL signals.

11. A circuit arrangement according to claim 10, wherein said first voltage level shifter is configured of ECL logic circuitry.

12. A circuit arrangement for interfacing first, parallel format, positive polarity TTL signals, the binary states of which transition at a first frequency between first and second voltage levels, to second, serial format, negative polarity ECL signals, the binary states of which transition at a second frequency, higher than said first frequency, between third and fourth voltage levels comprising:

a parallel-to-serial shift register, to respective parallel inputs of which said first, parallel format TTL signals are coupled, said shift register producing, at a serial output thereof, third signals the binary states of which transition at said second frequency between fifth and sixth voltage levels of said first polarity, said fifth and sixth voltage levels being larger than said first and second voltage levels and a voltage swing corresponding to that between said third and fourth voltage levels;

a first voltage level shifter, configured of ECL logic circuitry and coupled to receive the third signals produced by said shift register, said first voltage level shifter producing fourth signals of said first polarity and said second frequency, the binary states of said fourth signals switching at a voltage level corresponding to that at which said first signals switch between the binary states thereof; and

a second, TTL-ECL voltage level shifter, coupled to receive said fourth signals and shifting the voltage levels of the binary states thereof to negative polarity ECL levels.

13. A circuit arrangement according to claim 12, wherein each of said shift register and said first voltage level shifter is powered exclusively by a positive polarity power supply and said second TTL-ECL voltage level shifter is powered at each of said positive and negative voltage polarities.

14. A method of converting first, parallel format, positive polarity TTL signals, the binary states of which transition at a first frequency between first and second voltage levels, to second, serial format, negative polarity ECL signals, the binary states of which transition at a second frequency, higher than said first frequency, between third and fourth voltage levels comprising the steps of:

(a) coupling said first, parallel format TTL signals to respective parallel inputs of a parallel-to-serial shift register, said shift register producing, at a serial output thereof, third signals the binary states of which transition at said second frequency between fifth and sixth voltage levels of said first polarity, said fifth and sixth voltage levels being larger than said first and second voltage levels and a voltage swing corresponding to that between said third and fourth voltage levels;

(b) coupling said third signals to a first voltage level shifter which produces fourth signals of said first polarity and said second frequency, the binary states of said fourth signals switching at a voltage level corresponding to that at which said first signals switch between the binary states thereof; and

(c) coupling said fourth signals to a second TTL-ECL voltage level shifter which produces said serial format, negative polarity ECL signals.

15. A method according to claim 14, wherein each of said shift register and said first voltage level shifter is powered exclusively by a positive polarity power supply and said second TTL-ECL voltage level shifter is powered at each of said positive and negative voltage polarities.

16. A method according to claim 15, wherein said first voltage level shifter is configured of ECL logic circuitry.