Semiconductor integrated circuit configured by using polycell technique

• US 4,974,049 A
• Filed: 04/07/1988
• Issued: 11/27/1990
• Est. Priority Date: 03/08/1984
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Murakami, Hiroaki, Kondoh, Hitoshi, Sueda, Akihiro
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Clark, S. V.
• Application Number:
  US07/180,675
• Time in Patent Office: 964 Days
• Field of Search: 357/42, 357/45, 357/59, 357/71, 357/68
• US Class Current: 257/204
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor integrated circuit device configurated by using a polycell technique in which the wiring between the cell arrays is provided by two aluminum layers. The layers are insulated from each other by an insulator.

Claims

1. A semiconductor integrated circuit device configurated by using a polycell technique, comprising:

a plurality of cell arrays each extending in a first direction;

wiring regions each of which is provided between each two adjacent cell arrays;

a first unit cell included in one of said cell arrays;

a second unit cell included in one of the cell arrays which adjoins a first wiring region adjacent to the cell array including said first unit cell;

a third unit cell included in a cell array which is separated by at least one cell array from the cell array included said first unit cell;

a first metal wiring layer formed by extending an output wiring layer of said first unit cell into the first wiring region in a second direction perpendicular to said cell arrays;

a second metal wiring layer positioned at a level different from said first metal wiring layer and extending within the first wiring region in the first direction;

a first contact region connecting the first metal wiring layer to the second metal wiring layer;

a first polysilicon wiring layer formed by extending an input wiring layer of said second unit cell into the first wiring region in the second direction;

.

a second contact region connecting said second metal wiring layer to said first polysilicon wiring layer;

a through wiring layer formed of metal and being flush with said first metal wiring layer, said through wiring layer extending in the second direction above the at least one cell array between the cell array including said first unit cell and the cell array including said third unit cell;

a third contact region connecting said second metal wiring layer to said through wiring layer;

a third metal wiring layer flush with said second metal wiring layer and extending in the first direction into a second wiring region adjoining the cell array including said third unit cell;

a fourth contact region connecting said through wiring layer to said third metal wiring layer;

a second polysilicon wiring layer flush with said first polysilicon wiring layer and formed by extending an input wiring layer of the third unit cell into the second wiring region in the second direction; and

a fifth contact region connecting said third metal wiring layer to said second polysilicon wiring layer.

2. A device according to claim 1, wherein said second and third metal wiring layers constitute one layer of a double-layer wiring structure containing aluminum, and said first metal wiring layer and said through wiring layer constitute the other layer of the double-layer wiring structure.

3. A device according to claim 2, wherein said second and third metal wiring layers constitute a lower layer of the double-layer wiring structure, and said first metal wiring layer and said through wiring layer constitute an upper layer of the double-layer wiring structure.

4. A device according to claim 2, wherein said first metal wiring layer and said through wiring layer constitute a lower layer of the double-layer wiring structure, and said second and third metal wiring layers constitute an upper layer of the double-layer wiring structure.

5. A CMOS type semiconductor integrated circuit device configurated by using a polycell technique, comprising:

a plurality of cell arrays each extending in a first direction;

wiring regions each of which is provided between each two adjacent cell arrays;

a unit cell included in one of said cell arrays;

a semiconductor substrate which has a major surface and on which said unit cell is formed;

a well region formed within the major surface of said semiconductor substrate;

a function circuit included in said unit cell and comprising MOS transistors formed in the semiconductor substrate and the well region, said MOS transistors having gate electrodes formed on the well region in said unit cell and on the semiconductor substrate with a first insulating layer interposed therebetween;

a second insulating layer formed on the gate electrode and the first insulating layer;

a first metal wiring layer formed on the second insulating layer;

a first contact region formed in the second insulating layer in the proximity of a boundary between a side end portion of the well region and the semiconductor substrate and connecting the gate electrode to the first metal wiring layer;

a second metal wiring layer formed on the first metal wiring layer with a third insulating layer interposed therebetween; and

a second contact region formed in the third insulating layer in the proximity of a boundary between the well region and the semiconductor substrate and connecting the first metal wiring layer to the second metal wiring layer.

6. A device according to claim 5, wherein said first and second contact regions are located on the boundary between the side end portion of the well region and the semiconductor substrate and are aligned in a direction perpendicular to the major surface of the semiconductor substrate.

7. A device according to claim 5, wherein a distance between the side end portion of said well region and a remoter edge of the first and second contact regions is shorter than a value obtained by adding a distance between the side end portion of said well region and a prospective region for forming source and drain regions and said gate electrode to a value twice the width required for connecting said first and second metal wiring layers and said gate electrode.

8. A device according to claim 5, wherein said first and second metal wiring layers are each made of a layer containing aluminum.