Semiconductor device package with circuit board and resin

• US 4,974,057 A
• Filed: 01/09/1989
• Issued: 11/27/1990
• Est. Priority Date: 10/31/1986
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tazima, Akira
• Primary Examiner(s): Mintel, William
• Application Number:
  US07/296,392
• Time in Patent Office: 687 Days
• Field of Search: 357/54, 357/72, 357/69, 357/70, 357/75, 357/76, 357/71, 357/68, 357/80, 357/81, 357/74, 174/52.2
• US Class Current: 257/693
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/10689 : Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor device package having a semiconductor element of elements sealed in resin wherein a plurality of resin types different in function are used for sealing in which the more expensive resins are selectively used in forming thin covering layers for the semiconductor element and other components of the device, and the less expensive resin is used in a larger amount as an outer cover of a molded package. In another aspect of the semiconductor device package, bonding pads are provided at least in the active region of the semiconductor element or elements for wireless bonding of the semiconductor element to a circuit board. A stacked type semiconductor device package is also proposed wherein a plurality of semiconductor devices are stacked one atop the other, at least one of which has outer leads of longer length than the outer leads of the other semiconductor devices.

Claims

1. A semiconductor device package comprising:

a circuit board having a plurality of electrical contact areas provided thereon and being provided with at least one component thereon for performing an electrical function;

a semiconductor chip disposed in vertical registration with said circuit board and having an electrically active region thereon for performing electrical functions;

a plurality of bonding pads provided at least in said electrically active region of said semiconductor chip, said bonding pads being in engagement with respective electrical contact areas on said circuit board for electrically connecting the electrically active region of said semiconductor chip to said circuit board;

a lead frame having an inner lead frame portion disposed about the periphery of said circuit board and being in engagement with respective contact areas on said circuit board so as to be electrically connected to said circuit board and to said semiconductor chip via said circuit board, said lead frame including an outer lead frame portion comprising a plurality of conductive leads respectively connected at one end thereof to the inner lead frame portion and extending outwardly with respect to said circuit board and said semiconductor chip;

resin means encapsulating said circuit board, said semiconductor chip, and the inner lead frame portion of said lead frame to provide a wireless hermetically sealed package; and

said conductive leads of said outer lead frame portion being disposed outwardly of said encapsulating resin means.

2. A semiconductor device package as set forth in claim 1, wherein at least some of said electrical contact areas on said circuit board are bump electrodes projecting upwardly from said circuit board;

and

said bonding pads on said semiconductor chip being in engagement with said bump electrodes provided on said circuit board.

3. A semiconductor device package as set forth in claim 2, wherein said plurality of bonding pads on said semiconductor chip are arranged in a matrix of rows and columns of bonding pads in the electrically active region of said semiconductor chip.

4. A semiconductor device package as set forth in claim 3, further including a moisture-resistant metal coating disposed on each of said plurality of bonding pads.

5. A semiconductor device package as set forth in claim 1, wherein each of said semiconductor chip and said circuit board comprises the same chemical species of semiconductor material;

and

said circuit board including additional circuit elements formed thereon for operation in conjunction with the electrically active region of said semiconductor chip.

6. A semiconductor device package as set forth in claim 1, wherein said resin means comprises a plurality of different resins having different functions disposed on said semiconductor chip in coating relationship thereabout, said plurality of different resins including:

a thin layer of moisture-proof resin coating said semiconductor chip,

a thin layer of low stress resin covering said layer of moisture-proof resin, and

an outer layer of resin covering said layer of low stress resin;

said outer layer of resin being relatively inexpensive as compared to the thin layers of moisture-proof resin and low stress resin;

said outer layer of resin being relatively thick in relation to the thin layers of moisture-proof resin and low stress resin.

7. A semiconductor device package as set forth in claim 6, wherein said low stress resin is disposed at least around the connection end of individual conductive leads of the outer lead frame portion to the inner lead frame portion of said lead frame.

8. A semiconductor device package as set forth in claim 2, wherein said inner lead frame portion comprises a plurality of beam leads in engagement with respective contact areas on said circuit board.

9. A semiconductor device package as set forth in claim 8, further including conductive bumps on each of said beam leads of said inner lead frame portion projecting therefrom;

and

said conductive pumps of said beam leads being in engagement with respective contact areas on said circuit board.

10. A semiconductor device package as set forth in claim 9, wherein said lead frame comprises a main metallic body portion,

a metallic foil layer covering said metallic body portion, and

an intermediate metallic reinforcing layer interposed between said main metallic body portion and said metallic foil portion;

said metallic foil portion and said metallic reinforcing layer extending inwardly of said main metallic body portion of said lead frame in defining said beam leads of said inner lead frame portion with said conductive bumps of said beam leads being formed in said metallic foil layer.

11. A semiconductor device package as set forth in claim 3, wherein said lead frame is provided with a plurality of notches int eh inner lead frame portion thereof encapsulated by said resin means;

and

said notches in said inner lead frame portion being respectively of a size comparable to the size of individual resin grains of said encapsulating resin means for enhancing adherence of said encapsulating resin to said lead frame.

12. A semiconductor device package as set forth in claim 11, wherein said inner lead frame portion comprises a plurality of beam leads in engagement with respective contact areas on said circuit board.

13. A semiconductor device package as set forth in claim 12, further including conductive bumps on each of said beam leads of said inner lead frame portion projecting therefrom;

and

said conductive bumps of said beam leads being in engagement with respective contact areas on said circuit board.