Variable delay branch system

• US 4,974,155 A
• Filed: 08/15/1988
• Issued: 11/27/1990
• Est. Priority Date: 08/15/1988
• Status: Expired due to Fees

• Current Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Original Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Inventors: Dulong, Carole, Leclerc, Jean-Yves, Scaglia, Patrick
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/231,928
• Time in Patent Office: 834 Days
• Field of Search: 364/200 MS File
• US Class Current: 712/219
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution

Abstract

In a pipeline computer, current instructions executed in sequence are monitored for conditional and unconditional branch commands, as well as the readiness of condition codes, the meeting of branch conditions and split commands. A branch command initiates an interval of delay which affords prefetching target instructions while using pipeline contents to prevent a pipeline break and avoid lost time. Detection of a branch command actuates a register to store a sequence of target instructions. Unless a branch command is conditional, subsequent detection (delayed) of a split command shifts the stored target instructions into operation as the current instructions. For a conditional branch command, a jump or split to the target instructions is performed only if the condition is met. Otherwise the current instruction sequence is restored pending another branch command. Dual instruction registers, program counters and address registers alternate to accommodate branch jumps with considerable time savings by effective programming.

Claims

1. A process for a pipeline computer operation of branching from an existing sequence of instructions to a branch sequence of instructions under control of data in said existing sequence of instructions, the process including the steps of:

fetching instructions of said existing sequence and detecting a branch command in an instruction of the existing sequence to designate a branch instruction;

fetching said branch instruction to initiate a branch sequence of instructions;

executing instructions of said existing sequence of instructions to detect a split command in an instruction of the existing sequence indicating a time to branch; and

branching from said existing sequence of instructions to said branch sequence of instructions under control of said split command to establish said branch sequence of instructions for execution as the existing sequence of instructions.

2. A process according to claim 1 wherein said split command comprises a single bit in an instruction.

3. A process according to claim 1 wherein said sequence of instructions are advanced by incrementing a program counter.

4. A process according to claim 1 wherein said instructions include encoded signals for execution comprising operand addresses and split bit for said split command.

5. A process according to claim 1 including further steps of setting a condition for a branch and testing for said condition to provide further signals for controlling said split. PG,23

6. A branch structure for use with a pipeline computer including an instruction source for providing sequences of instructions, certain of which instructions include branch commands or split commands, and means for executing said instructions of a sequence, said system comprising:

instruction storage means for receiving current and target sequences of instructions from said instruction source and supplying instructions identified as the current sequence to said means for executing said instructions;

means controlled by a branch command in an instruction to store a target sequence of instructions in said instruction storage; and

means controlled by the occurrence of a split command in an instruction to shift said instruction storage from supplying said current sequence of instructions to supply said target sequence of instructions which target sequence of instructions accordingly is established as the current sequence of instructions.

7. A branch structure according to claim 6 wherein said instruction storage means further includes program counter means for tallying current and target program counts.

8. A branch structure according to claim 6 wherein said instruction storage means further includes program means for storing current and target addresses.

9. A branch structure according to claim 6 further including detection means operative with said means for executing instructions for detecting the occurrence of a branch command in an instruction.

10. A branch structure according to claim 6 further including detection means operative with said means for executing instructions for detecting the occurrence of a split bit in a command instruction.

11. A branch structure according to claim 6 further including detection means operative with said means for executing instructions for detecting the occurrence of a conditional branch command in an instruction and further including means for detecting the meeting of the specified condition.

12. A branch structure according to claim 11 further including detection means operative with said means for executing instructions for detecting the readiness of condition codes imposed by a branch command instruction.

13. A structure according to claim 6 wherein said instruction storage comprises a pair of first-in- first-out registers for alternately storing said current sequences of instructions.

14. A branch structure according to claim 6 wherein said instruction source takes the form of an instruction pipeline and said instruction storage means includes means for specifying addresses to said instruction pipeline.

15. A branch structure for use with a pipeline computer including an instruction source for providing sequences of instructions, certain of which instructions include branch commands or split commands, and means for executing said instructions of a sequence, said system comprising:

a first set of processor elements including a first instruction buffer, a first address register and a first program counter;

a second set of processor elements including a second instruction buffer, a second address register and a second program counter;

control means for advancing a current sequence of instructions by the operation of one of said first or second sets of processor elements;

branch means for detecting a branch command in said current sequence of instructions to specify a branch operation by setting a target sequence of instructions in said other of said first or second sets of processor elements;

split means for detecting a split command in said current sequence of instructions to specify implementing a previously detected branch command; and

means to implement a branch from said current sequence of instructions to said target sequence of instructions under control of said branch means and said split means.

16. A branch structure according to claim 15 further including condition means for detecting that branch conditions have been met and wherein said means to implement a branch is further under control of said condition means.