Maximum length pseudo-random test pattern generator via feedback network modification

• US 4,974,184 A
• Filed: 04/19/1990
• Issued: 11/27/1990
• Est. Priority Date: 05/05/1988
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Avra, Lanae
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Mai, Tan V.
• Application Number:
  US07/512,048
• Time in Patent Office: 222 Days
• Field of Search: 364/717, 331/78, 380/46, 371/25, 371/27
• US Class Current: 708/252
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G06F 7/582 Pseudo-random number generators

Abstract

A system and method for generating 2ⁿ test patterns is disclosed. The system utilizes a linear feedback shift register (LFSR) to generate a sequence of 2ⁿ -1 test patterns. In addition, the system includes apparatus external to the shift register which generates a 2ⁿ th test pattern. A switching circuit is employed to insert the 2ⁿ th test pattern into the sequence of test patterns. Therefore, a 2ⁿ test pattern sequence is generated. The test pattern sequence produced is pseudo-random in nature. The system further includes an output for providing a test pattern; such output could be used for the testing of a very large scale integration (VSLI) sub-system such as read only memory (ROM). A method utilizing the techniques embodied in the system is also disclosed.

Claims

1. An exhaustive test pattern generator for generating 2ⁿ test patterns, comprising:

(a) feedback shift register means comprising a feedback network logically coupled to only a single input of a shift register for generating a sequence of 2ⁿ -1 test patterns;

(b) means external to the feedback shift register means for generating a 2ⁿ th test pattern and for inserting the 2ⁿ th test pattern into the sequence of 2ⁿ -1 test patterns; and

(c) output means for providing the sequence of 2ⁿ test patterns.

2. The test pattern generator of claim 1 wherein the feedback shift register means comprises means for generating a test pattern sequence which is pseudo-random in nature.

3. The test pattern generator of claim 1 wherein the feedback shift register means comprises initializing means for setting the initial test pattern of the sequence generated by the feedback shift register means.

4. The test pattern generator of claim 1 wherein the combination of the feedback network and shift register operate as a linear feedback shift register.

5. The test pattern generator of claim 1 wherein the means external to the feedback shift register means logically comprises a multiplexer and additional combinational logic.

6. The test pattern generator of claim 1 wherein the feedback shift register means comprises a series of bistable multivibrators logically serially connected together to form a shift register.

7. The test pattern generator of claim 6 wherein the means external to the feedback shift register means logically comprises a multiplexer and additional combinational logic.

8. The test pattern generator of claim 7 wherein the additional combinational logic comprises means for providing to the multiplexer a selecting signal comprised of a logical AND of a plurality of outputs of the bi-stable multivibrators

9. The test pattern generator of claim 7 wherein the additional combinational logic comprises means for logically coupling the output of the last bi-stable multivibrator of the feedback shift register means to an input of the multiplexer.

10. The test pattern generator of claim 7 wherein the additional combinational logic comprises means for logically coupling the inverted output of the last bi-stable multivibrator of the feedback shift register means to an input of the multiplexer.

11. A test pattern generator for generating 2ⁿ test patterns, comprising:

(a) shift register means for storing a series of test pattern signals as a test pattern;

(b) feedback network means logically coupled to an output of the shift register means for generating a sequence of 2ⁿ -1 test pattern signals;

(c) circuit means logically coupled to an output of the shift register means for generating a 2ⁿ th test pattern signal;

(d) switching means logically coupled to the shift register means, the feedback network means and the circuit means for inserting the 2ⁿ th test pattern signal into the sequence of test pattern signals generated by the feedback network means and for serially providing the sequence of 2ⁿ test pattern signals to only a single input of the shift register means; and

(e) output means for providing the sequence of 2ⁿ test patterns.

12. The test pattern generator of claim 11 wherein the sequence of 2ⁿ test pattern signals serially provided to only a single input of the shift register means is pseudo-random in nature.

13. The test pattern generator of claim 11 wherein the shift register means comprises initializing means for setting the initial test pattern of the sequence stored by the shift register means.

14. The test pattern generator of claim 11 wherein the combination of the shift register means and the feedback network means operate as a linear feedback shift register.

15. The test pattern generator of claim 11 wherein the shift register means comprises a series of bi-stable multivibrators logically serially connected together to form a shift register.

16. The test pattern generator of claim 15 wherein the circuit means comprises the non-inverted output of the last bi-stable multivibrator of the shift register means logically coupled to an input of the switching means.

17. The test pattern generator of claim 15 wherein the circuit means comprises the inverted output of the last bi-stable multi-vibrator of the shift register means logically coupled to an input of the switching means.

18. The test pattern generator of claim 15 wherein the switching means logically comprises a multiplexer and means for providing to the multiplexer a selecting signal comprising the logical AND of a plurality of outputs of the bi-stable multi-vibrators.

19. The test pattern generator of claim 18 wherein the plurality of outputs of the bi-stable multi-vibrators comprise non-inverted outputs of the bi-stable multi-vibrators.

20. The test pattern generator of claim 18 wherein the plurality of outputs of the bi-stable multi-vibrators comprise inverted outputs of the bi-stable multi-vibrators.

21. The test pattern generator of claim 18 wherein the plurality of outputs of the bi-stable multi-vibrators comprise non-inverted and inverted outputs of the bi-stable multi-vibrators.

22. The test pattern generator of claim 11 wherein:

(a) the feedback network means logically couples exclusively to outputs of the shift register means;

(b) the circuit means logically couples exclusively to outputs of the shift register means; and

(c) the switching means provides the test pattern signals exclusively to a most significant input of the shift register means.

23. A method for generating 2ⁿ test patterns for use in exhaustive testing, comprising the steps of:

(a) checking a selecting signal for a "true" or a "false" signal;

(b) if the selecting signal is "true", generating with a feedback shift register device comprising a feedback network logically coupled to only a single input of a shift register one of 2ⁿ -1 possible test patterns;

(c) if the selecting signal is "false", generating with means external to the feedback shift register device a 2ⁿ th test pattern not included in the 2ⁿ -1 possible test patterns generated by the feedback shift register device;

(d) outputting the test pattern to an external element;

(e) feeding back the outputted test pattern through the feedback network; and

(f) repeating steps (a) through (e) to generate an exhaustive test sequence of 2ⁿ unique test patterns.

24. The method of claim 23 wherein "true" is equivalent to a binary "1" state and "false" is equivalent to a binary "0" state.

25. The method of claim 23 wherein "true" is equivalent to a binary "0" state and "false" is equivalent to a binary "1" state.

26. A test pattern generator for generating 2ⁿ test patterns, comprising:

(a) shift register means comprising a plurality of bistable multi-vibrators logically coupled in series from an output signal of a first bi-stable multi-vibrator to an input signal of a second bi-stable multi-vibrator for storing a series of test pattern signals as one of 2ⁿ test patterns, the plurality of bi-stable multi-vibrators including initializing means for setting the initial test pattern signals stored by the bi-stable multi-vibrators so that the shift register means can be set to a predetermined test pattern at the beginning of test pattern generation;

(b) feedback means comprising combinational logic logically coupled to a plurality of output signals form the bistable multi-vibrators for generating an XOR function of the output signals and for providing to an output the generated function as one of a sequence of 2ⁿ -1 test pattern signals so that a sequence of 2ⁿ -1 unique test pattern signals is generated;

(c) circuit means logically coupled to one of the output signals of one of the bi-stable multi-vibrators in the shift register means for providing to an output the 2ⁿ th test pattern signal;

(d) switching means for inserting the 2ⁿ th test pattern signal provided by the output of the circuit means into the sequence of signals generated by the output of the feedback means so that a sequence of 2ⁿ test patterns is generated and for serially providing the sequence of 2ⁿ test pattern signals to only a single input of the shift register means; and

(e) output means logically coupled to at least one of the bi-stable multi-vibrator outputs for providing the sequence of 2ⁿ test patterns.

27. A test pattern generator of claim 26 wherein the switching means comprises:

(a) circuit element means for providing to an output a logical AND function of a plurality of flip-flop outputs; and

(b) a multiplexer comprising;

(i) an input logically coupled to the output of the feedback means;

(ii) an input logically coupled to the output of the circuit means;

(iii) an output logically coupled to only a single input of one of the bi-stable multi-vibrators in the register means; and

(iv) a selecting input logically coupled to the output of the circuit element means for selecting one of the multiplexer inputs as the multiplexer output.