Modular digital signal processing system
First Claim
1. A dual convolver circuit for convolving a sequence of values X(m) wherein m are successive integers, to obtain an output sequence Y(m) according to the equation ##EQU31## the circuit comprising:
- a plurality of scalar multipliers ek, k=0 to L-1, where L is a positive integer greater than 1, for respectively multiplying each value X(m) by a scalar value ek, each of said scaler multipliers having an output port;
a first adder AD0 having a first input port connected to the output port of the scalar e0, a second input port and first and second output ports;
a plurality of adders ADk, k=1 to L-1, the (k+1)th adder ADk having a first input port connected to the output port of the scaler multiplier ek, second and third input ports and first and second output ports;
an Lth adder ADL-1 having a first input port connected to the output port of the scalar eL-1, a second input port and first and second output ports;
a plurality of delay and switch means Vk, k=0 to L-3, respectively disposed between the (k+1)th and (k+2)th adders ADk and ADk+1, each delay and switch means Vk including a first two sample delay element Zk1-2, a second two sample delay element Zk2-2, a first switch SWk1 alternately connecting the first output port of the (k+1)th adder ADk to an input port of the first two sample delay element Zk1-2 in a first state of the circuit and the second input port of the (k+1)th adder ADk to an output port of the second two sample delay element Zk2-2 in a second state of the circuit, and a second switch SWk2 alternately connecting the third input port of the (k+2)th adder ADk+1 to an output port of the first two sample delay element Zk1-2 in the first state of the circuit and the second outport port of the (k+2)th adder ADk+1 to an input port of the second two sample delay element Zk2-2 in the second state of the circuit;
an (L-1)th delay and switch means VL-2, disposed between the (L-1)th and Lth adders ADL-2 and ADL-1, and including a first two sample delay element Z.sub.(L-2)1-2 and a second two sample delay element Z.sub.(L-2)2-2, a first switch SW.sub.(L-2)1 alternately connecting the first output port of the (L-1)th adder ADL-2 to an input port of the first two sample delay element Z.sub.(L-2)1-2 in the first state of the circuit and the second input port of the (L-1)th adder ADL-2 to an output port of the second two sample delay element Z.sub.(L-2)2-2 in the second state of the circuit, and a second switch SW.sub.(L-2)2 alternately connecting the second input port of the Lth adder ADL-1 to an output port of the first two sample delay element Z.sub.(L-2)1-2 in the first state of the circuit and the second output port of the Lth adder ADL-1 to an input port of the second two sample delay element Z.sub.(L-2)2-2 in the second state of the circuit; and
means for controlling the first and second switches of said delay and switch means Vk, k=0 to L-2 to alternate the first and second states of the circuit with successive value X(m) such that the first state corresponds to values X(m) when m is an even integer and the second state corresponds to values X(m) when m is an odd integer the first through (L-1)th adders ADk, k=0 to L-2 providing at the second output port thereof a sum of input values at the first and second input ports thereof when the circuit is in said second state, the first through (L-1)th adders ADk, k=0 to L-2 providing at the second output port thereof a sum of input values at the first and second input ports thereof when the circuit is in said second state, the Lth adder ADL-1 providing at the second output port thereof the value at the first input port thereof when the circuit is in said second state, the second through (L-
1)th adders ADk, k=1 to L-2 providing at the first output port thereof a sum of input values at the first and third input ports thereof when the circuit is in said first state, the Lth adder ADL, providing at the first output port thereof a sum of input values at the first and second input ports thereof when the circuit is in said first state, the first adder AD0 providing at the first output port thereof the value at the first input port thereof when the circuit is in said first state.
1 Assignment
0 Petitions
Accused Products
Abstract
A modular digital signal processor system for calculating "wavelet-analysis transformations" and "wavelet-synthesis transformations" of one-dimensional numerical data and multi-dimensional numerical data for solving speech processing and other problems. The system includes one or more "dual-convolver" components, "analyzer-adjunct" components, "synthesizer-adjunct" components, "de-interleaver components" and "interleaver components", and specific configurations of these components for implementing specific functions. Each dual-convolver is capable of loading a finite number of numerical values into its coefficient registers and subsequently performing two convolution operations on input sequences of numerical values to produce an output sequence of numerical values. Two dual-convolvers are configured with an analyzer adjunct or synthesizer adjunct to respectively build a single stage analyzer or synthesizer. Analyzers and synthesizers are configured in conjunction with interleavers and de-interleaver components to build wavelet sub-band processors capable of decomposing one-dimensional sequences of numerical data or multi-dimensional arrays of numerical data into constituent wavelets and to synthesize the original sequences or arrays from their constituent wavelets. Synthesizers are configured with interleavers to build function generators capable of calculating functions including wavelet functions to within any specified degree of detail.
105 Citations
37 Claims
-
1. A dual convolver circuit for convolving a sequence of values X(m) wherein m are successive integers, to obtain an output sequence Y(m) according to the equation ##EQU31## the circuit comprising:
- a plurality of scalar multipliers ek, k=0 to L-1, where L is a positive integer greater than 1, for respectively multiplying each value X(m) by a scalar value ek, each of said scaler multipliers having an output port;
a first adder AD0 having a first input port connected to the output port of the scalar e0, a second input port and first and second output ports; a plurality of adders ADk, k=1 to L-1, the (k+1)th adder ADk having a first input port connected to the output port of the scaler multiplier ek, second and third input ports and first and second output ports; an Lth adder ADL-1 having a first input port connected to the output port of the scalar eL-1, a second input port and first and second output ports; a plurality of delay and switch means Vk, k=0 to L-3, respectively disposed between the (k+1)th and (k+2)th adders ADk and ADk+1, each delay and switch means Vk including a first two sample delay element Zk1-2, a second two sample delay element Zk2-2, a first switch SWk1 alternately connecting the first output port of the (k+1)th adder ADk to an input port of the first two sample delay element Zk1-2 in a first state of the circuit and the second input port of the (k+1)th adder ADk to an output port of the second two sample delay element Zk2-2 in a second state of the circuit, and a second switch SWk2 alternately connecting the third input port of the (k+2)th adder ADk+1 to an output port of the first two sample delay element Zk1-2 in the first state of the circuit and the second outport port of the (k+2)th adder ADk+1 to an input port of the second two sample delay element Zk2-2 in the second state of the circuit; an (L-1)th delay and switch means VL-2, disposed between the (L-1)th and Lth adders ADL-2 and ADL-1, and including a first two sample delay element Z.sub.(L-2)1-2 and a second two sample delay element Z.sub.(L-2)2-2, a first switch SW.sub.(L-2)1 alternately connecting the first output port of the (L-1)th adder ADL-2 to an input port of the first two sample delay element Z.sub.(L-2)1-2 in the first state of the circuit and the second input port of the (L-1)th adder ADL-2 to an output port of the second two sample delay element Z.sub.(L-2)2-2 in the second state of the circuit, and a second switch SW.sub.(L-2)2 alternately connecting the second input port of the Lth adder ADL-1 to an output port of the first two sample delay element Z.sub.(L-2)1-2 in the first state of the circuit and the second output port of the Lth adder ADL-1 to an input port of the second two sample delay element Z.sub.(L-2)2-2 in the second state of the circuit; and means for controlling the first and second switches of said delay and switch means Vk, k=0 to L-2 to alternate the first and second states of the circuit with successive value X(m) such that the first state corresponds to values X(m) when m is an even integer and the second state corresponds to values X(m) when m is an odd integer the first through (L-1)th adders ADk, k=0 to L-2 providing at the second output port thereof a sum of input values at the first and second input ports thereof when the circuit is in said second state, the first through (L-1)th adders ADk, k=0 to L-2 providing at the second output port thereof a sum of input values at the first and second input ports thereof when the circuit is in said second state, the Lth adder ADL-1 providing at the second output port thereof the value at the first input port thereof when the circuit is in said second state, the second through (L-
1)th adders ADk, k=1 to L-2 providing at the first output port thereof a sum of input values at the first and third input ports thereof when the circuit is in said first state, the Lth adder ADL, providing at the first output port thereof a sum of input values at the first and second input ports thereof when the circuit is in said first state, the first adder AD0 providing at the first output port thereof the value at the first input port thereof when the circuit is in said first state. - View Dependent Claims (2)
- a plurality of scalar multipliers ek, k=0 to L-1, where L is a positive integer greater than 1, for respectively multiplying each value X(m) by a scalar value ek, each of said scaler multipliers having an output port;
-
3. A signal processor for processing a sequence of input values X.sup.(1) (m) wherein m are successive integers, comprising:
-
an analyzer means having a sequence input port and a sequence output port; and a de-interleaver means having an input port and first and second output ports, a first de-interleaver connecting means for connecting the input port of the de-interleaver means to the output port of the analyzer means; and a second de-interleaver connecting means for connecting the first output port of the de-interleaver means to the input port of the analyzer means; said analyzer means comprising means, responsive to the sequence of input values X.sup.(1) (m) and sequences of input values X.sup.(i) (m) for i=2 to J, J a positive integer greater than one, wherein m are successive integers, at its input port for outputting at its output port sequences of output values Y.sup.(i) (m) for i=1 to J, given by ##EQU32## where Ni for i=1 to J are even positive integers, and k, i=1 to J, k=0 to Ni -1, are numerical constants which, for each i, satisfy for all even integers j the equation ##EQU33## said de-interleaver means having means, responsive to the sequence of values Y.sup.(i) (m), i=1 to J-1, at its input port, for outputting at the first output port a sequence of values X.sup.(i+1) (m) equal to Y.sup.(i) (2m) and for outputting at the second output port a sequence of values S.sup.(i) (m) equal to Y.sup.(i) (2m+1). - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A signal processor for processing an ordered array of input values X.sup.(1) (m,n) wherein m and n each represent successive integers, comprising:
-
an analyzer means having an array input port and first and second array output ports; and a de-interleaver means having an input port and first and second output ports, a first de-interleaver connecting means for connecting the input port of the de-interleaver means to the first array output port of the analyzer means; a second de-interleaver connecting means for connecting the first output port of the de-interleaver means to the array input port of the analyzer means; said analyzer means comprising means, responsive to an array of input values X.sup.(1) (m,n) at its array input port for all i=1 to J, J a positive integer greater than one, wherein m are successive integers, for outputting at its first array output port for i=1 to J-1 and at its second array output port for i=J an array of output values Y.sup.(i) (m,n) given by ##EQU40## where Mi and Ni, i=1 to J, are even positive integers, and α
j, j=0 to Mi -1 and β
k, k=0 to N-1, are numerical constants which, for each i, satisfy for all even integers s and t the equations ##EQU41## said de-interleaver means having means, responsive to the array of values Y.sup.(i) (m,n), i=1 to J-1, at its input port, for outputting at the first output port the array of values X.sup.(i+1) (m,n) equal to Y.sup.(i) (2m,2n) and for outputting at the second output port arrays of values S.sup.(i) OO (m, n), equal to Y.sup.(i) (2m+1,2n+1), (m,n) equal to Y.sup.(i) (2m+1,2n), and S.sup.(i)EO (m,n) equal to Y.sup.(i) (2m,2n+1). - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
33. A single stage wavelet analyzer circuit for processing a sequence of values X(m) wherein m are successive integers, to obtain an output sequence Y(m) according to the equation ##EQU50## where N is a positive even integer, the wavelet analyzer circuit comprising:
-
first and second dual-convolver circuits and an analyzer-adjunct circuit, said first dual convolver circuit comprising means for convolving the sequence of values X(m) to obtain a first sequence Y1 (m) at an output port thereof according to the equation ##EQU51## and said second dual convolver circuit comprising means for convolving the sequence of values X(m) to obtain a second sequence Y2 (m) at an output port thereof according to the equation ##EQU52## said analyzer-adjunct circuit comprising means, having input ports respectively connected to the output ports of said first and second dual convolver circuits, for processing the first and second sequences Y1 (m) and Y2 (m) to obtain the sequence Y(m) according to the relation
space="preserve" listing-type="equation">Y(m)=Y.sub.1 (m-2)+Y.sub.2 (m-1) for m even
space="preserve" listing-type="equation">Y(m)=-Y.sub.1 (m)+Y.sub.2 (m-1) for m odd; andthe values β
k, k=0 to N-1, are numerical constants which satisfy for all even integers j the equation ##EQU53## - View Dependent Claims (34)
-
-
35. A single stage wavelet synthesizer circuit for processing a sequence of values W(m) wherein m designates success integers, to obtain an output sequence Z(m) according to the equation ##EQU54## where N is a positive even integer, the circuit comprising:
- first and second dual-convolvers circuits and an analyzer-adjunct circuit, said first dual convolver comprising means for convolving the sequence of values W(m) to obtain a first sequence Z1 (m) at an output port thereof according to the equation ##EQU55## and said second dual convolver comprising means for convolving the sequence of values W(m) to obtain a second sequence Z2 (m) at an output port thereof according to the equation ##EQU56## said synthesizer-adjunct circuit comprising means, having input ports respectively connected to the output ports of said first and second dual convolver circuits, for processing the first and second sequences Z1 (m) and Z2 (m) to obtain the sequence Z(m) according to the relation
space="preserve" listing-type="equation">Z(m)=Z.sub.1 (m)+Z.sub.2 (m-1) for m even
space="preserve" listing-type="equation">Z(m)=-Z.sub.1 (m-2)+Z.sub.2 (m-1) for m oddwherein the values β
k, k=0 to N-1 are numerical constants which satisfy for all even integers j the equation ##EQU57## - View Dependent Claims (36)
- first and second dual-convolvers circuits and an analyzer-adjunct circuit, said first dual convolver comprising means for convolving the sequence of values W(m) to obtain a first sequence Z1 (m) at an output port thereof according to the equation ##EQU55## and said second dual convolver comprising means for convolving the sequence of values W(m) to obtain a second sequence Z2 (m) at an output port thereof according to the equation ##EQU56## said synthesizer-adjunct circuit comprising means, having input ports respectively connected to the output ports of said first and second dual convolver circuits, for processing the first and second sequences Z1 (m) and Z2 (m) to obtain the sequence Z(m) according to the relation
-
37. A function generator, comprising:
-
a source of null sequences; a plurality, J in number, of successive synthesizer circuits Si, where i=1 to J, each having an input port and an output port; and J-1 interleaver circuits Ii, where i=1 to J-1, each having an output port and a data input port and a null input port, for all i, i=1 to J-1, the output port of the interleaver Ii is connected to the input port of the synthesizer circuit Si, the data input port of the interleaver Ii is connected to the output port of the synthesizer circuit Si+1, and the null input port of the interleaver Ii is connected to the output port of the processing means Pi ;
each synthesizer circuit Si comprising means, responsive to a sequence of input values W.sup.(i) (m) at its input port wherein m represents success integers, for generating and outputting at its output port a sequence of output values Z.sup.(i) (m) given by ##EQU58## each interleaver circuit Ii having means for outputting at the output port the sequence of values W.sup.(i) (m), being equal to Z.sup.(i+1) (m/2) for m even and equal to T.sup.(i) ((m-1)/2) for m odd, the output port of the processing means PJ being connected to input port of the synthesizer circuit SJ so that the sequence W.sup.(J) (m) input to the input port of the synthesizer SJ is the output sequence of the processing means PJ, whereby if the effect of the processing means Pi, i=1 to J is such that the sequences T.sup.(i) (m) are respectively approximately equal to the sequences S.sup.(i) (m), then the sequences Z.sup.(i) (m) are approximately equal to the respective sequences ##EQU59##
-
Specification