High speed communication processing system
First Claim
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1. A communication processing system comprising:
- a processor bus;
a plurality of network processors, each network processor connected to the processor bus;
a plurality of packet processors, each packet processor connected to the processor bus;
a plurality of switch matrices;
a plurality of network interfaces;
a plurality of interfaces to user input/output devices; and
bidirectional bus means includingmeans for connecting each switch matrix to each other switch matrix,means for connecting each packet processor to a switch matrix,means for connecting each network processor to a switch matrix,means for connecting each switch matrix to a portion of the user interfaces andmeans for connecting each switch matrix to a portion of the network interfaces.
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Abstract
A communications node for handling circuit and packet switching and capable of expansion to include multiple switching matrices, multiple network processors and multiple packet processors is disclosed. Each switch matrix has multipile I/O ports and communications with user interfaces, network interfaces and other system components via bidirectional data links. At least one switch matrix is connected via a bidirectional data link to a packet processor and a network processor. All processors are interconnected via a computer bus. Switch matrices are connected to each other either by a backplane bus or via bidirectional data links.
46 Citations
4 Claims
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1. A communication processing system comprising:
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a processor bus; a plurality of network processors, each network processor connected to the processor bus; a plurality of packet processors, each packet processor connected to the processor bus; a plurality of switch matrices; a plurality of network interfaces; a plurality of interfaces to user input/output devices; and bidirectional bus means including means for connecting each switch matrix to each other switch matrix, means for connecting each packet processor to a switch matrix, means for connecting each network processor to a switch matrix, means for connecting each switch matrix to a portion of the user interfaces and means for connecting each switch matrix to a portion of the network interfaces.
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2. A communication processing system comprising:
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a processor bus; a network processor connected to the processor bus; a packet processor connected to the processor bus; a plurality of switch matrices; a plurality of network interfaces for receiving data from and providing data to the switch matrices, a plurality of user interfaces for receiving data from and providing data to the switch matrices, and bidirectional bus means including means for connecting each switch matrix to the network processor, means for connecting each switch matrix to the packet processor, means for connecting each of the switch matrix to a portion of the network interfaces and means for connecting each of the switch matrices to a portion of the user interfaces.
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3. A communication processing system comprising:
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processor bus means; a plurality of network processors, each network processor connected to the processor bus; a plurality of packet processors, each packet processor connected to the processor bus; a switch matrix; a network interface; a user interface; bidirectional bus means including means for connecting the switch matrix to each network processor, means for connecting the switch matrix to each packet processor, means for connecting the switch matrix to the network interface and means for connecting the switch matrix to the user interface.
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4. A digital cross-connect system comprising:
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a processor bus; a plurality of network processors, each network processor connected to the processor bus; a plurality of packet processors, each packet processor connected to the processor bus; a plurality of switch matrices; a plurality of network interfaces; and bidirectional bus means including means for connecting each switch matrix to each other switch matrix, means for connecting each packet processor to a switch matrix, means for connecting each network processor to a switch matrix, and means for connecting each switch matrix to a portion of the network interfaces.
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Specification
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Current AssigneeData General Corp. (Dell Technologies Inc.)
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Original AssigneeData General Corp. (Dell Technologies Inc.)
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InventorsAlmond, Gary, Mostafa, Asghar, Lee, Fred S.
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Primary Examiner(s)Yusko, Donald J.
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Assistant Examiner(s)Holloway, III, Edwin C.
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Application NumberUS07/103,611Time in Patent Office1,160 DaysField of Search340/825.79, 340/825.03, 340/825.04, 370/85, 370/94, 370/60, 370/64, 370/60.1, 370/85.1, 370/94.1US Class Current340/2.27CPC Class CodesH04L 12/64 Hybrid switching systemsH04Q 11/0407 using a stored programme co...
