Complementary semiconductor device

• US 4,975,757 A
• Filed: 10/20/1987
• Issued: 12/04/1990
• Est. Priority Date: 07/04/1977
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suzuki, Yasoji, Matsuki, Koji, Egawa, Hideharu
• Primary Examiner(s): MUNSON, GENE M
• Application Number:
  US07/111,122
• Time in Patent Office: 1,141 Days
• Field of Search: 357/42, 357/59, 357/91
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Claims

1. A complementary semiconductor device comprising:

a semiconductor substrate of one conductivity type having a low impurity concentration;

non-abutting P- and N-type semiconductor regions formed in said substrate and having an impurity concentration higher than that of said substrate;

an N-channel type silicon gate field effect transistor including source and drain regions formed in said P-type semiconductor region, and a gate region including a gate electrode comprising a polycrystalline silicon layer of one conductivity type; and

a P-channel type silicon gate field effect transistor including source and drain regions formed in said N-type semiconductor region, and a gate region including a gate electrode comprising a polycrystalline silicon layer;

wherein said P- and N-type semiconductor regions are physically separated apart from each other by a portion of said semiconductor substrate.

2. A complementary semiconductor device according to claim 1, in which the gate regions include an oxide layer formed under the polycrystalline silicon layer.

3. A complementary semiconductor device according to claim 2, in which said semiconductor substrate has an impurity concentration of about 10¹³ to 10¹⁴ atoms/cm³.

4. A complementary semiconductor device according to claim 3, in which said P- and N-type semiconductor regions have an impurity concentration of about 10¹⁵ atoms/cm³.

5. A complementary semiconductor device according to claim 1 in which the polycrystalline silicon layers are of an N-conductivity type.

6. A complementary semiconductor device according to claim 1 in which the polycrystalline silicon layers are of a P-conductivity type.