Highly integrated circuit and method for the production thereof

• US 4,975,765 A
• Filed: 07/07/1989
• Issued: 12/04/1990
• Est. Priority Date: 07/22/1988
• Status: Expired due to Fees

• Current Assignee: Contraves AG (Rheinmetall AG)
• Original Assignee: Contraves AG (Rheinmetall AG)
• Inventors: Ackermann, Karl-Peter, Berner, Gianni
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Clark, S. V.
• Application Number:
  US07/376,674
• Time in Patent Office: 515 Days
• Field of Search: 357/70, 357/74, 357/80, 174/52.4
• US Class Current: 257/737
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

In a highly integrated circuit the semiconductor chip (8) is fastened on a substrate (17) which projects on all sides only a few millimeters beyond the semiconductor chip (8). For Full dynamic testing of the circuit before insertion, connections are provided which are arranged outside the projecting substrate edge (23) with a sufficiently large grid spacing.

In a first embodiment (FIG. 2D) "lost" test connections (5) are used which are separated after testing.

In a second embodiment (FIG. 3E), contact areas in the form of bumps (21) are used for testing which are arranged on the underside of the through-holes (18) lying in the chip mounting area.

In this manner it is possible to realize a circuit with greatly reduced space requirement, which at the same time can be fully tested dynamically before insertion.

Claims

1. A highly integrated circuit, especially for a multi-chip module, comprising:

a flat semiconductor chip with a chip area and a plurality of chip connections arranged with a first grid spacing;

a flat substrate with a top side and an underside and a substrate area which is greater than the chip area;

on the top side of the substrate a mounting area, on which the semiconductor chip is arranged;

the substrate projecting on all sides with a substrate edge beyond the semiconductor chip; and

there being provided on the top side of the substrate first connecting areas with a second grid spacing which is essentially equal to the first grid spacing; and

the chip connections being conductively connected to the first connecting areas;

wherein the circuit is surrounded by an additional substrate edge provided for testing the semiconductor chip, where said additional substrate edge carries conductor tracks and test connections, extends beyond the chip area, and is separable after testing; and

the circuit extends to a substrate area which is greater than the chip area, so that the substrate edge is of a width of only a few millimeters.

7. A highly integrated circuit as claimed in claim 1, wherein the edge width is less than 2 mm.

8. A highly integrated circuit as claimed in claim 1, wherein

on the top side of the substrate conductor tracks extend to the edges of the substrate starting from the first connecting areas;

and

there are provided at the edges of the substrate second connecting areas which are connected to the first connecting areas by the conductor tracks.

9. A highly integrated circuit as claimed in claim 1, wherein

there are provided inside the mounting area in the substrate through-metallized through-holes which conductively connect the top side of the substrate to its underside, and have on the underside contact areas in the form of bumps;

the through-holes are arranged with a third grid spacing which is considerably larger than the first grid spacing; and

at least on the top side of the substrate conductor tracks extend to the through-holes starting from the first connecting areas.

10. A highly integrated circuit as claimed in claim 8, wherein the first connecting areas are connected to the chip connections by means of connecting wires and the semiconductor chip is covered by a sealing compound.

11. A highly integrated circuit as claimed in claim 9, wherein the first connecting areas are connected to the chip connections by means of connecting wires and the semiconductor chip is covered by a sealing compound.

12. A highly integrated circuit as claimed in claim 9, wherein the first connecting areas are arranged in mirror-image fashion to the chip connections are soldered directly thereto.

13. A highly integrated circuit as claimed in claim 9, wherein the first connecting areas are arranged in mirror-image fashion to the chip connections and are soldered directly thereto.

2. A highly integrated circuit, especially for a multi-chip module, comprising:

a flat semiconductor chip with a chip area and a plurality of chip connections arranged with a first grid spacing;

a flat substrate with a top side and an underside and a substrate area which is greater than the chip area;

on the top side of the substrate a mounting area, on which the semiconductor chip is arranged;

the substrate projecting on all sides with a substrate edge beyond the semiconductor chip; and

there being provided on the top side of the substrate first connecting areas with a second grid spacing which is essentially equal to the first grid spacing; and

the chip connections being conductively connected to the first connecting areas;

wherein

the substrate edge has an edge width less than 2 millimeters; and

connections for testing the semiconductor chip are provided outside of the substrate edge.

3. A highly integrated circuit as claimed in claim 2, wherein

on the top side of the substrate conductor tracks extend to the edges of the substrate starting from the first connecting areas;

and

there are provided at the edges of the substrate second connecting areas which are connected to the first connecting areas by the conductor tracks.

4. A highly integrated circuit as claimed in claim 2, wherein

there are provided inside the mounting area in the substrate through-metallized through-holes which conductively connect the top side of the substrate to its underside, and have on the underside contact areas in the form of bumps;

the through-holes are arranged with a third grid spacing which is considerably larger than the first grid spacing; and

at least on the top side of the substrate conductor tracks extend to the through-holes starting from the first connecting areas.

5. A highly integrated circuit as claimed in either of claims 3 and 4, wherein the first connecting areas are connected to the chip connections by means of connecting wires and the semiconductor chip is covered by a sealing compound.

6. A highly integrated circuit as claimed in either of claims 3 or 4, wherein the first connecting areas are arranged in mirror-image fashion to the chip connections and are soldered directly thereto.