Field effect controlled, bipolar power semiconductor component with silicide layer

• US 4,975,782 A
• Filed: 02/22/1989
• Issued: 12/04/1990
• Est. Priority Date: 02/22/1988
• Status: Expired due to Fees

• Current Assignee: Asea Brown Boveri Ltd (ABB Limited)
• Original Assignee: Asea Brown Boveri Ltd (ABB Limited)
• Inventors: Bauer, Friedhelm
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US07/313,521
• Time in Patent Office: 650 Days
• Field of Search: 357/37, 357/38, 357/39, 357/67 S, 357/34, 357/59 G, 357/1 I, 357/86, 357/23.4, 357/51
• US Class Current: 257/144
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

In an IGT (Insulated Gate Transistor), the short-circuiting between the n-type regions (5c) and the p-type regions (4b) of the n-type emitter layer or p-type base layer respectively is produced by a buried conducting layer (12), specifically in the form of a metal silicide layer. Regardless of the spacing between cathode contact (8) and gate (7), the length of the n-type regions (5c) can thereby be reduced to such an extent that latching-up of the component is virtually impossible.

Claims

1. A field effect controlled, bipolar semiconductor device, comprising

(a) a disk-like semiconductor substrate having first and second parallel main surfaces, wherein the first of said main surfaces is connected to an anode (A), and the second of said main surfaces is connected to a cathode (K);

(b) two successive layers provided within said semiconductor substrate extending in parallel with said main surfaces, wherein a first of said successive layers comprises a p-type emitter layer which abuts upon said first main surface, and the second of said successive layers comprises an n-type base layer which abuts upon said second main surface;

(c) a plurality of individual p-type regions constituting a p-type base layer and being embedded side by side in said n-type base layer at said second main surface, and being separated from each other by gaps, wherein said n-type base layer emerges in said gaps at said second main surface of said semiconductor substrate;

(d) a plurality of individual n-type regions being embedded in each of said p-type regions in a manner such that each said p-type region emerges at said second main surface of said semiconductor substrate at outer sides of said p-type region and between the n-type regions embedded therein; and

(e) a gate-cathode structure with alternatingly disposed gate electrodes and cathode contacts provided on said second main surface, wherein one of said cathode contacts is disposed above each of said p-type regions and conductively connected to all n-type regions of the associated p-type region, and makes contact to said p-type region between said n-type regions, and wherein above each of said gaps between adjacent of said p-type regions is disposed one of said gate electrodes and which is electrically insulated from said semiconductor substrate and which covers those parts of said adjacent p-type regions which emerge at said second main surface; and

(f) a first conductive layer provided for conductive connection between each of said cathode contacts and the associated n-type regions, said first conductive layer extending on said second main surface of said semiconductor substrate from between respective ones of said cathode contacts and said associated p-type region to all n-type regions of said p-type region, said first conductive layer covering said n-type regions partially and being composed of a metal silicide.

2. The device as claimed in claim 1, wherein said first conductive layer has a composition and comprises a metal selected from the group consisting of titanium, tungsten, tantalum and cobalt.

3. The device as claimed in claim 2, wherein said first conductive layer is isolated from said cathode contact where said first conductive layer covers said n-type regions.

4. The device as claimed in claim 3, wherein said gate electrodes are composed of polysilicon and are provided with a second conductive layer on each of their upper sides, said second conductive layer having a composition similar to the composition of said first conductive layer.

5. The device as claimed in claim 1, comprising:

a p⁺ -type zone disposed in each case between the n-type regions embedded in each of said p-type regions, said p³⁰ -type zone extending from said second main surface of said semiconductor substrate through said p-type region into said n-type base layer.